DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
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PIN DESCRIPTION
PIN NAME FUNCTION
1 A1 Device Address Bit 1
2 A2 Device Address Bit 2
3 PIO3 PIO line #3
4 PIO2 PIO line #2
5 PIO1 PIO line #1
6 PIO0 PIO line #0
7 V
CC
Power Supply Input
8 MRZ Master Reset (active-low). Performs a reset of the serial interface and the PIOs without
power-cycling the device.
9 WP Write Protect input, to be connected to V
CC
or GND. When connected to V
CC
, the entire
EEPROM array is write-protected. Normal read/write access when connected to GND.
Changing the pin state during a write access will cause unpredictable results.
10 SCL I²C/SMBus serial clock input; must be tied to V
CC
through a pullup resistor.
11 SDA I²C/SMBus bidirectional serial data line; must be tied to V
CC
through a pullup resistor.
12 GND Ground supply for the device.
EP GND Exposed Paddle. Solder evenly to the board’s ground plane for proper operation. See
Application Note 3273
for additional information.
OVERVIEW
The DS28CZ04 consists of a serial I²C/SMBus interface, 4Kb of EEPROM and four bidirectional PIO channels, as
shown in the block diagram in Figure 1. The device communicates with a host processor through its I²C interface in
standard-mode or in fast-mode; the user can switch the interface from I²C bus to SMBus mode. Two address pins
allow 4 DS28CZ04 to reside on the same bus segment. A Master reset pin permits a full device reset without power
cycling.
The device has a memory range of 512 bytes, organized as two segments (lower half, upper half) of 256 bytes
(Figure 2). The memory map and device addressing is compatible with SFF-8472 Digital Diagnostic address
assignments. The entire EEPROM can be write-protected by tying the WP pin to V
CC
. The PIO pins can be
accessed through one address (= single-address mode) or through separate addresses (= multi-address mode).
PIO direct access addressing allows fast generation of data patterns and fast sampling.
The DS28CZ04 includes several EEPROM registers for the user to select whether the device powers up in SFF
mode and to define the power-on default conditions for individual PIO output state (high, low, in output mode),
individual PIO data direction (in, out), individual PIO output type (push-pull, open drain), individual PIO read bit
inversion (true, false). Once powered up, the PIO settings can be overwritten through SRAM registers without
affecting the power-on defaults.
