DS28CZ04G-4+T Datasheet DS28CZ04G-4+T, DS28CZ04G-4+ | P16-P18

DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO

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Figure 7. SRAM and PIO Writing

Memory Location PIO Multi-Address Mode PIO Single-Address Mode

Address Function SRAM Write PIO Direct SRAM Write PIO Direct

00h to 77h Memory

78h Reserved

79h Reserved

7Ah Register

7Bh Register

7Ch PIO R/W

7Dh PIO R/W

7Eh PIO R/W

7Fh PIO R/W

Lower Half

80h to FFh Memory

Upper

Half

00h to FFh Memory

When writing to a PIO, as shown in Figure 8, any state change is triggered by the SCL pulse that the master

generates for the acknowledge bit of byte written to the PIO Read/Write Access Register. After the output transition

time t

is expired, the state change is completed. In PIO Single-Address mode all PIOs change their state

approximately at the same time; in this mode the fastest rate for a PIO to change its state is f

SCL

/9. In PIO Multi-

Address Mode each PIO is accessed individually; in this mode when writing in an endless loop the fastest rate for a

PIO to change its state is f

SCL

/36. Transfer of data can be stopped at any moment by a STOP condition. When this

occurs, data present at the last acknowledged phase is valid.

Figure 8. PIO Write Access Timing

SRAM Write

SCL

PIO

MSB DATA1 LSB A MSB DATA2 LSB A MSB DATA3 LSB AMSB (7Bh) data LSB A

DATA1 DATA2

PIO Direct

S A6 A5 A4 A3 A2 A1 P0 0 A MSB PIO Address LSB A MSB DATA1 LSB A MSB DATA2 LSB A

SCL

PIO

DATA1

Reading Memory and PIOs

If the DS28CZ04 is addressed in read access mode, the read pointer determines the location from which the

master will start reading. The read pointer is set when the DS28CZ04 is accessed in write access mode, either for

DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO

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writing data or through a dummy write. At power-on the read pointer is reset to address 00h of the lower half of the

memory. A description on how the read pointer is affected during write accesses is included in Table 1A. In

contrast to write accesses where the memory is updated in small blocks of 8 or 16 bytes, all 512 bytes are readable

in a single read access. Only two cases need to be distinguished: normal read and PIO direct. Table 2A explains

the cases in detail.

Table 2A. Read Access

READING WHILE DEVICE IS NOT BUSY

PIO Mode Read Pointer SMBus or I²C Bus Mode

Anywhere excluding

device address = A0h,

memory address from

7Ch to 7Fh (normal read)

Slave address is acknowledged; data is delivered;

read pointer increments, eventually crossing from lower half to

upper half of the memory, and wraps around from upper half

FFh to lower half 00h.

Multi-

Address

Device address = A0h,

memory address from

7Ch to 7Fh (PIO direct)

Slave address is acknowledged; data is delivered;

read pointer increments and wraps around from 7Fh to 7Ch,

staying in the lower half of memory.

Anywhere excluding

device address = A0h,

memory address = 7Ch

(normal read)

Slave address is acknowledged; data is delivered;

read pointer increments, eventually crossing from lower half to

upper half of the memory, and wraps around from upper half

FFh to lower half 00h.

Single-

Address

Device address = A0h,

memory address = 7Ch

(PIO direct)

Slave address is acknowledged; data is delivered;

read pointer stays at 7Ch.

The PIO Address Mode in conjunction with the initial read pointer position determines the sequence in which the

addresses are accessed. Figure 9 illustrates the possible cases.

Figure 9. Memory and PIO Reading

Memory Location PIO Multi-Address Mode PIO Single-Address Mode

Address Function Normal Read PIO Direct Normal Read PIO Direct

00h to 77h Memory

78h Reserved

79h Reserved

7Ah Register

7Bh Register

7Ch PIO R/W

7Dh PIO R/W

7Eh PIO R/W

7Fh PIO R/W

Lower Half

80h to FFh Memory

Upper

Half

00h to FFh Memory

DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO

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The common characteristic in both normal read cases is a starting address anywhere in the memory excluding

any address used for PIO access. The read pointer increments after every byte read. This way a series of read

accesses reveals memory data of consecutive addresses, without any duplications or gaps. When reading from

reserved areas the master receives FFh bytes. When the end of the upper half of the memory is reached (device

address A2h, address FFh) the read pointer wraps around to the start of the lower half of the memory (device

address A0h, address 00h). When the end of the lower half of the memory is reached, the read pointer continues at

the start of the upper half of the memory. To change the read address, the master has to address the DS28CZ04 in

write access mode and specify a new memory address.

The common characteristic in both PIO direct cases is a starting address within the address range used for PIO

access. In PIO Multi-Address Mode, there are four such addresses (7Ch to 7Fh); each PIO occupies its own

address. After a byte is sent to the master, the read pointer increments to the next PIO and eventually wraps

around to 7Ch. In PIO Single-Address Mode, there is exactly one address (7Ch) that is shared by all PIOs.

Consequently, the master can continue reading, but the read pointer stays at 7Ch.

When reading from a PIO, as shown in Figure 10, the sampling takes place on the falling SCL edge of the 2

-last

bit before the acknowledge bit. With PIO direct mode, the first sample is taken 3 SCL cycles earlier, i. e., during the

transmission of the A3 bit of the slave address. To be correctly assessed, the PIO state must not changed during

the t

and t

interval. In PIO Single-Address mode all PIOs are sampled simultaneously; in this mode with PIO

direct access the fastest sample rate for a PIO is f

SCL

/9. In PIO Multi-Address Mode each PIO is sampled individu-

ally; in this mode with PIO direct access the fastest sample rate for a PIO is f

SCL

/36. Transfer of data can be

stopped at any moment by a STOP condition. When this occurs, data from the last sampling instance is lost.

Figure 10. PIO Read Access Timing

Normal Read

MSB DATA2 LSB A MSB DATA3 LSB A MSB DATA4 LSB A

Sampling

Sampling Sampling

PIO

SCL

MSB (7Bh) data LSB A

DATA1 DATA2

DATA4

DATA3

DATA5

PIO Direct

S A6 A5 A4 A3 A2 A1 P0 1 A MSB DATA1 LSB A MSB DATA3 LSB A MSB DATA4 LSB A

Sampling

Sampling Sampling

PIO

SCL

DATA1 DATA2

DATA4

DATA3

DATA5

With revision A1 devices, the sampling always takes place on the falling SCL edge of the last bit before the

acknowledge bit. The sampled data, however, is reported to the master one byte late, as shown in Figure 10A. The

first sample of PIO data that the master receives in PIO direct access should be discarded since its timing relative

to the transmission of the slave address is undefined. Any application firmware developed for revision A1 devices is

fully compatible to newer devices.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P22

DS28CZ04G-4+T

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DS28CZ04G-4+T

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