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DS28CZ04G-4+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
7 of 22
BIT DESCRIPTION BIT(S) DEFINITION
PIM0: Power-On Read
Inversion PIO0
b0
Power-on default state of read-inversion bit of PIO0; 0 ⇒ no inversion,
1 ⇒ inversion
PIM1: Power-On Read
Inversion PIO1
b1
Power-on default state of read-inversion bit of PIO1; 0 ⇒ no inversion,
1 ⇒ inversion
PIM2: Power-On Read
Inversion PIO2
b2
Power-on default state of read-inversion bit of PIO2; 0 ⇒ no inversion,
1 ⇒ inversion
PIM3: Power-On Read
Inversion PIO3
b3
Power-on default state of read-inversion bit of PIO3; 0 ⇒ no inversion,
1 ⇒ inversion
POT0: Power-On Output
Type PIO0
b4
Power-on default output type of PIO0; 0 ⇒ push-pull, 1 ⇒ open drain
POT1: Power-On Output
Type PIO1
b5
Power-on default output type of PIO1; 0 ⇒ push-pull, 1 ⇒ open drain
POT2: Power-On Output
Type PIO2
b6
Power-on default output type of PIO2; 0 ⇒ push-pull, 1 ⇒ open drain
POT3: Power-On Output
Type PIO3
b7
Power-on default output type of PIO3; 0 ⇒ push-pull, 1 ⇒ open drain
Direction and Control/Status Register (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
7Ah
ADMD CM BUSY SFF DIR3 DIR2 DIR1 DIR0
There is general read and write access to this address. Bit 5 is read-only. The power-on default of bits 0 to 3 is
copied from memory address 76h (Device Address = A0h) bits 4 to 7, respectively.
BIT DESCRIPTION BIT(S) DEFINITION
DIR0: Direction PIO0 b0
Direction of PIO0; 0 ⇒ output, 1 ⇒ input
DIR1: Direction PIO1 b1
Direction of PIO1; 0 ⇒ output, 1 ⇒ input
DIR2: Direction PIO2 b2
Direction of PIO2; 0 ⇒ output, 1 ⇒ input
DIR3: Direction PIO3 b3
Direction of PIO3; 0 ⇒ output, 1 ⇒ input
SFF: SFF Mode Bit b4
SFF Mode control; 0 ⇒ SFF Mode off, 1 ⇒ SFF Mode on.
See Memory Map (Device Address = A2h) and SFF Optional Status
Register description for details. The SFF Mode Bit, when set to 1, does
not change the direction of PIO0 and PIO1 to input.
BUSY: EEPROM Busy
Indicator
b5
If this bit reads 1, an EEPROM write cycle (A0h or A2h Device Address)
is in progress. (SMBus mode only; reads 0 in I²C bus mode)
CM: Communication
Mode
b6
Selects mode for the serial communication interface.
0: I²C bus mode (power-on default)
1: SMBus mode
ADMD: PIO Address
Mode
b7
Selects Address Mode for PIO Read/Write access. See PIO Read/Write
Access Registers for details.
0: Multi-Address Mode (power-on default)
1: Single-Address Mode
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
8 of 22
PIO Read-Inversion and Output Type (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
7Bh
OT3 OT2 OT1 OT0 IMSK3 IMSK2 IMSK1 IMSK0
There is general read and write access to this address. The power-on default is copied from memory address 77h
(Device Address = A0h).
BIT DESCRIPTION BIT(S) DEFINITION
IMSK0: Read-inversion
control of PIO0
b0
0 ⇒ no inversion, 1 ⇒ data read from PIO0 is inverted
IMSK1: Read-inversion
control of PIO1
b1
0 ⇒ no inversion, 1 ⇒ data read from PIO1 is inverted
IMSK2: Read-inversion
control of PIO2
b2
0 ⇒ no inversion, 1 ⇒ data read from PIO2 is inverted
IMSK3: Read-inversion
control of PIO3
b3
0 ⇒ no inversion, 1 ⇒ data read from PIO3 is inverted
OT0: Output Type of
PIO0
b4
0: ⇒ Push-Pull, 1 ⇒ Open Drain
OT1: Output Type of
PIO1
b5
0: ⇒ Push-Pull, 1 ⇒ Open Drain
OT2: Output Type of
PIO2
b6
0: ⇒ Push-Pull, 1 ⇒ Open Drain
OT3: Output Type of
PIO3
b7
0: ⇒ Push-Pull, 1 ⇒ Open Drain
PIO Read/Write Access Registers (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0 PIO Address Mode
IV3 IV2 IV1 IV0 OV3 OV2 OV1 OV0 Single
7Ch
1 1 1 IV0 1 1 1 OV0 Multi
00h (no function) Single
7Dh
1 1 1 IV1 1 1 1 OV1 Multi
00h (no function) Single
7Eh
1 1 1 IV2 1 1 1 OV2 Multi
00h (no function) Single
7Fh
1 1 1 IV3 1 1 1 OV3 Multi
There is general read and write access to these registers. Bits shown as 1 have no function; their state cannot be
changed.
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
9 of 22
BIT DESCRIPTION BIT(S) DEFINITION
OV0: Output Value of
PIO0
⎯
Logic output state of PIO0 if DIR0 = 0 (output)
OV1: Output Value of
PIO1
⎯
Logic output state of PIO1 if DIR1 = 0 (output)
OV2: Output Value of
PIO2
⎯
Logic output state of PIO2 if DIR2 = 0 (output)
OV3: Output Value of
PIO3
⎯
Logic output state of PIO3 if DIR3 = 0 (output)
IV0: Input Value of PIO0
⎯
Logic state read from PIO0 XOR’ed with IMSK0
IV1: Input Value of PIO1
⎯
Logic state read from PIO1 XOR’ed with IMSK1
IV2: Input Value of PIO2
⎯
Logic state read from PIO2 XOR’ed with IMSK2
IV3: Input Value of PIO3
⎯
Logic state read from PIO3 XOR’ed with IMSK3
Figure 3 shows a simplified schematic of a PIO. The flip flops are accessed through the PIO R/W Access Registers
and memory addresses 7Ah and 7Bh (Device Address = A0h). They are initialized at power-up or during reset
according to the data stored at memory addresses 76h and 77h (Device Address = A0h). When a PIO is configured
as input, the PIO output is tri-stated (high impedance). When a PIO is configured as output, the PIO input is the
same as the output state XOR'ed with the corresponding read inversion bit.
Figure 3. PIO Simplified Schematic
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
DIRn
OVn
OTn
Vcc
D Q
CLK
IMSKn
PIOn Pin
to Serial Interface
IVn
OTn
from Serial Interface
CLK
DIRn
from Serial Interface
OVn
from Serial Interface
IMSKn
from Serial Interface
Note
: OTn, DIRn, OVn and IMSKn are
nonvolatile based on power-on register
values (memory addresses 76h and 77h,
device address A0h)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

DS28CZ04G-4+T

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Manufacturer:
Maxim Integrated
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