1
X9241A
Quad Digital Controlled Potentionmeters (XDCP™)
Non-Volatile/Low Power/2-Wire/64 Taps
The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
microcircuit.
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 nonvolatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array through the switches. Power up
recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
Four potentiometers in one package
2-wire serial interface
Register oriented format
- Direct read/write/transfer of wiper positions
- Store as many as four positions per potentiometer
Terminal Voltages: +5V, -3.0V
Cascade resistor arrays
Low power CMOS
High Reliability
- Endurance–100,000 data changes per bit per register
- Register data retention–100 years
16-bytes of nonvolatile memory
3 resistor array values
-2k10k50kor combination
- Cascadable for values of 4kto 200k
Resolution: 64 taps each pot
20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC
packages
Pb-free available (RoHS compliant)
Block Diagram
DATA
8
R1
R0
R3
R2
V
H0
/R
H0
V
L0
/R
L0
V
W0
/R
W0
WIPER
COUNTER
REGISTER
(WCR)
V
H1
/R
H1
V
L1
/R
L1
V
W1
/R
W1
REGISTER
ARRAY
POT 1
WIPER
COUNTER
REGISTER
(WCR)
R1
R0
R3
R2
SCL
SDA
A0
A1
A2
A3
INTERFACE
AND
CONTROL
CIRCUITRY
V
H2
/
V
L2
/R
L2
V
W2
/R
W2
V
H3
/R
H3
V
L3
/R
L3
V
W3
/R
W3
REGISTER
ARRAY
POT 2
WIPER
COUNTER
REGISTER
(WCR)
R1
R0
R3
R2
REGISTER
ARRAY
POT 3
WIPER
COUNTER
REGISTER
(WCR)
R1
R0
R3
R2
V
CC
V
SS
R
H2
Data Sheet FN8164.7August 17, 2015
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
2
FN8164.7
August 17, 2015
Ordering Information
PART NUMBER PART MARKING
V
CC
LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(k)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
X9241AMPZ (Note)
(No longer available,
recommended
replacement:
X9241AMSZT1)
X9241AMPZ 5 ±10% 2/10/50
Pot 0 = 2k
Pot 1 = 10k
Pot 2 = 10k
Pot 3 = 50k
0 to +70 20 Ld PDIP***
X9241AMPIZ (Note)
(No longer available,
recommended
replacement:
X9241AMSZT1)
X9241AMPIZ -40 to +85 20 Ld PDIP***
X9241AMSZ* (Note) X9241AMS Z 0 to +70 20 Ld SOIC
X9241AMSIZ* (Note) X9241AMSI Z -40 to +85 20 Ld SOIC
X9241AMVZ (Note) X9241AM VZ 0 to +70 20 Ld TSSOP
X9241AMVIZ* (Note) X9241AM VIZ -40 to +85 20 Ld TSSOP
X9241AWPIZ (Note) X9241AWPIZ 10
Pot 0 = 10k
Pot 1 = 10k
Pot 2 = 10k
Pot 3 = 10k
0 to +70 20 Ld PDIP
X9241AWSZ* (Note) X9241AWS Z 0 to +70 20 Ld SOIC
X9241AWSIZ* (Note) X9241AWSI Z -40 to +85 20 Ld SOIC
X9241AWVZ* (Note) X9241AW VZ 0 to +70 20 Ld TSSOP
X9241AWVIZ*
(Note) X9241AW VIZ -40 to +85 20 Ld TSSOP
X9241AYPZ (Note)
(No longer available,
recommended
replacement: X9241AYSIZ)
X9241AYPZ 2
Pot 0 = 2k
Pot 1 = 2k
Pot 2 = 2k
Pot 3 = 2k
0 to +70 20 Ld PDIP***
X9241AYSZ* (Note) X9241AYS Z 0 to +70 20 Ld SOIC
X9241AYSIZ* (Note) X9241AYSI Z -40 to +85 20 Ld SOIC
X9241AYVZ (Note)
(No longer available,
recommended
replacement: X9241AYVIZ)
X9241AY VZ 0 to +70 20 Ld TSSOP
X9241AYVIZ* (Note) X9241AY VIZ -40 to +85 20 Ld TSSOP
X9241AUPZ (Note) X9241AUPZ 5 ±10% 50
Pot 0 = 50k
Pot 1 = 50k
Pot 2 = 50k
Pot 3 = 50k
0 to +70 20 Ld PDIP***
X9241AUPIZ (Note) X9241AUPIZ -40 to +85 20 Ld PDIP***
X9241AUSZ* (Note) X9241AUS Z 0 to +70 20 Ld SOIC
X9241AUSIZ* (Note) X9241AUSI Z -40 to +85 20 Ld SOIC
X9241AUVZ* (Note)
(No longer available,
recommended
replacement:
X9241AUSZT1)
X9241AU VZ 0 to +70 20 Ld TSSOP
X9241AUVIZ* (Note) X9241AU VIZ -40 to +85 20 Ld TSSOP
*Add "T1" suffix for tape and reel.
***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
X9241A
3
FN8164.7
August 17, 2015
Pin Descriptions
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9241A.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-
ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the guidelines
for calculating typical values on the bus pull-up resistors
graph.
Address
The Address inputs are used to set the least significant
4-bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the Address
input in order to initiate communication with the X9241A.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
TO V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
TO V
L3
/R
L3
)
The R
H
and R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
/R
W
(V
W0
/R
W0
TO V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Pinout
X9241A
(20 LD DIP, SOIC, TSSOP)
TOP VIEW
Principles of Operation
The X9241A is a highly integrated microcircuit incorporating
four resistor arrays, their associated registers and counters
and the serial interface logic providing direct communication
between the host and the XDCP potentiometers.
Serial Interface
The X9241A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9241A will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
LOW
). SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
HIGH
). The X9241A continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8-bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the 8-bits of data. See Figure 7.
The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9241A will
respond with a final acknowledge.
Pin Names
SYMBOL DESCRIPTION
SCL Serial Clock
SDA Serial Data
A0 to A3 Address
V
W0
/R
W0
A0
A2
V
H1
/R
H1
SDA
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
A1
A3
SCL
X9241A
V
L0
/R
L0
V
H0
/R
H0
V
W1
/R
W1
V
L1
/R
L1
V
W3
/R
W3
V
L3
/R
L3
V
H3
/R
H3
V
W2
/R
W2
V
L2
/R
L2
V
H2
/R
H2
V
H0
/R
H0
to V
H3
/R
H3
,
V
L0
/R
L0
to V
L3
/R
L3
Potentiometer Pins (terminal equivalent)
V
W0
/R
W0
to V
W3
/R
W3
Potentiometer Pins (wiper equivalent)
Pin Names
SYMBOL DESCRIPTION
X9241A

X9241AUVIZT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs QD CMOS EEPOT 50KOHM S
Lifecycle:
New from this manufacturer.
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