X9241AUVIZT1 Datasheet X9241AYVIZ, X9241AWSZ, X9241AWVZT1 | P7-P9

FN8164.7

August 17, 2015

SCL FROM

DATA OUTPUT

FROM TRANSMITTER

STAR T

ACKNOWLEDGE

MASTER

DATA OUTPUT

FROM RECEIVER

FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER

X9241A

FN8164.7

August 17, 2015

Detailed Operation

All four XDCP potentiometers share the serial interface and

share a common architecture. Each potentiometer is

comprised of a resistor array, a Wiper Counter Register and

four Data Registers. A detailed discussion of the register

organization and array operation follows.

Wiper Counter Register

The X9241A contains four volatile Wiper Counter Registers

(WCR), one for each XDCP potentiometer. The WCR can be

envisioned as a 6-bit parallel and serial load counter with its

outputs decoded to select one of sixty-four switches along its

resistor array. The contents of the WCR can be altered in

four ways: it may be written directly by the host via the Write

WCR instruction (serial load); it may be written indirectly by

transferring the contents of one of four associated Data

Registers via the XFR Data Register instruction (parallel

load); it can be modified one step at a time by the

increment/decrement instruction; finally, it is loaded with the

contents of its Data Register zero (DR0) upon power-up.

The WCR is a volatile register; that is, its contents are lost

when the X9241A is powered-down. Although the register is

automatically loaded with the value in DR0 upon power-up, it

should be noted this may be different from the value present

at power-down.

Data Registers

Each potentiometer has four nonvolatile Data Registers.

These can be read or written directly by the host and data

can be transferred between any of the four Data Registers

and the WCR. It should be noted all operations changing

data in one of these registers is a nonvolatile operation and

will take a maximum of 10ms.

If the application does not require storage of multiple

settings for the potentiometer, these registers can be used

as regular memory locations that could possibly store

system parameters or user preference data.

SERIAL DATA PATH

FROM INTERFACE

CIRCUITRY

SERIAL

BUS

INPUT

PARALLEL

BUS

INPUT

WIPER

COUNTER

INC/DEC

LOGIC

UP/DN

CLK

MODIFIED SCL

UP/DN

IF WCR = 00[H] THEN V

= V

IF WCR = 3F[H] THEN V

= V

8 6

CASCADE

CONTROL

LOGIC

FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM

X9241A

FN8164.7

August 17, 2015

Cascade Mode

The X9241A provides a mechanism for cascading the

arrays. That is, the sixty-three resistor elements of one array

may be cascaded (linked) with the resistor elements of an

adjacent array. The V

of the higher order array must be

connected to the V

of the lower order array (See

Figure 9).

Cascade Control Bits

The data byte, for the three-byte commands, contains 6-bits

(LSBs) for defining the wiper position plus 2 high order bits,

CM (Cascade Mode) and DW (Disable Wiper, normal

operation).

The state of the CM bit (bit 7 of WCR) enables or disables

cascade mode. When the CM bit of the WCR is set to “0” the

potentiometer is in the normal operation mode. When the

CM bit of the WCR is set to “1” the potentiometer is

cascaded with its adjacent higher order potentiometer. For

example; if bit 7 of WCR2 is set to “1”, pot 2 will be cascaded

to pot 3.

The state of DW enables or disables the wiper. When the

DW bit (bit 6 of the WCR) is set to “0” the wiper is enabled;

when set to “1” the wiper is disabled. If the wiper is disabled,

the wiper terminal will be electrically isolated and float.

When operating in cascade mode V

, V

and the

wiper terminals of the cascaded arrays must be electrically

connected externally. All but one of the wipers must be

disabled. The user can alter the wiper position by writing

directly to the WCR or indirectly by transferring the contents

of the Data Registers to the WCR or by using the

Increment/Decrement command.

When using the Increment/Decrement command the wiper

position will automatically transition between arrays. The

current position of the wiper can be determined by reading

the WCR registers; if the DW bit is “0”, the wiper in that array

is active. If the current wiper position is to be maintained on

power-down a global XFR WCR to Data Register command

must be issued to store the position in NV memory before

power-down.

It is possible to connect three or all four potentiometers in

cascade mode. It is also possible to connect POT 3 to POT 0

as a cascade. The requirements for external connections of

, V

and the wipers are the same in these cases.

POT 0

WCR0

POT 1

WCR1

POT 2

WCR2

POT 3

WCR3

EXTERNAL

CONNECTION

FIGURE 9. CASCADING ARRAYS

X9241A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

X9241AUVIZT1

Mfr. #:

Buy X9241AUVIZT1

Manufacturer:

Renesas / Intersil

Description:

Digital Potentiometer ICs QD CMOS EEPOT 50KOHM S

Lifecycle:

New from this manufacturer.

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X9241AUVIZT1

X9241AUVIZT1

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