Crystal-to-0.7V Differential HCSL/
LVCMOS Frequency Synthesizer
841S012DI
Datasheet
©2016 Integrated Device Technology, Inc January 4, 20161
GENERAL DESCRIPTION
The 841S012DI is an optimized PCIe, sRIO and Gigabit Ethernet
Frequency Synthesizer and a member of high performance clock
solutions from IDT. The 841S012DI uses a 25MHz parallel resonant
crystal to generate 33.33MHz - 200MHz clock signals, replacing
multiple oscillators and fanout buffer solutions. The device supports
±0.25% center-spread, and -0.5% down-spread clocking with two
spread select pins (SSC[1:0]). The VCO operates at a frequency of
2GHz. The device has three output banks: Bank A with two 100MHz
– 250MHz HCSL outputs; Bank B with seven 33.33MHz – 200MHz
LVCMOS/ LVTTL outputs; and Bank C with one 33.33MHz – 200MHz
LVCMOS/LVTTL output.
All Banks A, B and C have their own dedicated frequency
select pins and can be independently set for the frequencies
mentioned above. The low jitter characteristic of the 841S012DI
makes it an ideal clock source for PCIe, sRIO and Gigabit Ethernet
applications. Designed for networking and industrial applications,
the 841S012DI can also drive the high-speed clock inputs of com-
munication processors, DSPs, switches and bridges.
FEATURES
Two 0.7V differential HCSL outputs (Bank A), confi gurable for
PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz)
clock signals
Eight LVCMOS/LVTTL outputs (Banks B/C),
18Ω typical output impedance
Two REF_OUT LVCMOS/LVTTL clock outputs,
23Ω typical output impedance
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or one LVCMOS/LVTTL single-ended refer-
ence clock input
Supports the following output frequencies:
HCSL Bank A: 100MHz, 125MHz, 200MHz and 250MHz
LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz,
100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz
VCO: 2GHz
Spread spectrum clock: ±0.25% center-spread (typical) and
-0.6% down-spread (typical)
PLL bypass and output enable
RMS period jitter: 10ps (typical), QAx/nQAx outputs
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
PIN ASSIGNMENT
15 16 17 18 19 20 21 22 23 24 25 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
36
37
38
39
40
41
42
35
34
33
32
31
30
29
V
DD_REFOUT
REF_OUT0
REF_OUT1
GND
GND
REF_IN
V
DD
V
DD
REF_SEL
XTAL_IN
XTAL_OUT
BYPASS
REF_OE
nMR
V
DDOC
QC
GND
QBC_OE
V
DDA
V
DDA
V
DD
GND
GND
IREF
QA0
nQA0
QA1
nQA1
GND
GND
SSC1
SSC0
F_SELB2
F_SELB1
F_SELB0
F_SELC2
F_SELC1
F_SELC0
F_SELA1
F_SELA0
QA_OE
V
DD
QB6
GND
QB5
V
DDOB
QB4
GND
QB3
V
DDOB
VDDOB
QB2
GND
QB1
QB0
V
DDOB
484950515253545556 47 46 45 44 43
ICS841S012DI
56-Lead VFQFN
8mm x 8mm x 0.925mm
package body
K Package
Top View
841S012DI Datasheet
©2016 Integrated Device Technology, Inc January 4, 20162
BLOCK DIAGRAM
0
1
1
0
PLL
VCO
2GHz
M =
÷
80
÷NA
÷NC
OSC
2
3
2
QA0
nQA0
QA1
nQA1
QB0
QC
QB1
QB2
QB3
QB4
QB5
QB6
REF_OUT0
REF_OUT1
QA_OE
F_SELA[1:0]
BYPASS
REF_IN
IREF
REF_OE
REF_SEL
nMR
SSC[1:0]
XTAL_IN
XTAL_OUT
25MHz
Pulldown
Pullup
3
F_SELC[2:0]
Pulldown
Pullup
QBC_OE
Pullup
F_SELB[2:0]
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Spread
Spectrum
÷NB
841S012DI Datasheet
©2016 Integrated Device Technology, Inc January 4, 20163
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1V
DD_REFOUT
Power Output supply pin for REF_OUT.
7, 14, 28, 29 V
DD
Power Core supply pins.
2,
3
REF_OUT0,
REF_OUT1
Output
Single-ended LVCMOS/LVTTL reference clock outputs.
23Ω typical output impedance.
4, 5, 15, 27, 35,
36, 40, 46, 50,
54
GND Power Power supply ground.
6 REF_IN Input Pulldown Single-ended LVCMOS/LVTTL reference clock input.
8 REF_SEL Input Pulldown
Reference select pin. When HIGH selects REF_IN. When LOW,
selects crystal. LVCMOS/LVTTL interface levels. See Table 3E.
9,
10
XTAL_IN, XTAL_
OUT
Input
Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.
External tuning capacitor must be used for proper operation.
11 BYPASS Input Pulldown
When HIGH bypasses PLL. When LOW, selects PLL.
LVCMOS/LVTTL interface levels. See Table 3J.
12 REF_OE Input Pulldown
Active HIGH REF_OUT enables/disables pin.
LVCMOS/LVTTL interface levels. See Table 3H.
13 nMR Input Pullup
Active LOW Master Reset. When logic LOW, the internal dividers are reset
and the outputs are in high impedance (HI-Z). When logic HIGH, the internal
dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3I.
16,
17
SSC1,
SSC0
Input Pullup SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D.
18,
19,
20
F_SELB2, F_
SELB1,
F_SELB0
Input Pulldown
Frequency select pins for QBx outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
21,
22,
23
F_SELC2, F_
SELC1,
F_SELC0
Input Pulldown
Frequency select pins for QC output. See Table 3C.
LVCMOS/LVTTL interface levels.
24,
25
F_SELA1, F_
SELA0
Input Pulldown
Frequency select pins for QAx/nQAx outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
26 QA_OE Input Pullup
Output enable pin for Bank A outputs. See Table 3F. LVCMOS/LVTTL inter-
face levels.
30, 31
32, 33
nQA1, QA1
nQA0, QA0
Output Differential Bank A clock outputs. HCSL interface levels.
34 IREF Output
External fi xed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode QAx/nQAx clock outputs.
37, 38 V
DDA
Power Analog supply pin.
39 QBC_OE Input Pullup
Output enable pin for Bank B and Bank C outputs.
LVCMOS/LVTTL Interface levels. See Table 3G.
41 QC Output
Single-ended Bank C clock output. LVCMOS/LVTTL interface levels.
18Ω typical output impedance.
42 V
DDOC
Power Output supply pin for QC LVCMOS output.
43, 48, 52, 56 V
DDOB
Power Output supply pins for QBx LVCMOS outputs.
44, 45,
47, 49,
51, 53, 55
QB0, QB1, QB2,
QB3, QB4, QB5,
QB6
Output
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
18Ω typical output impedance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

841S012DKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner MULTIRATE FEMTOCLOCK LVPE
Lifecycle:
New from this manufacturer.
Delivery:
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