841S012DI Datasheet
©2016 Integrated Device Technology, Inc January 4, 20167
TABLE 6. AC CHARACTERISTICS, V
DD
= V
DD_REFOUT
= V
DDOB
= V
DDOC
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency
QB[0:6] 33.33 200 MHz
QA[0:1]/nQA[0:1] 100 250 MHz
QC 33.33 200 MHz
tsk(b)
Bank Skew;
NOTE 1, 2
QB[0:6] 50 ps
QA[0:1]/nQA[0:1] 50 ps
tsk(o) Output Skew; NOTE 1, 3
across Banks B and C
(at Same Frequency)
160 ps
tjit(cc)
Cycle-to-Cycle
Jitter; NOTE 1
QA[0:1]/nQA[0:1]
All Outputs at Same Fre-
quency
65 ps
tjit(per) RMS Period Jitter
QA[0:1]/nQA[0:1]
REF_OE = 0, All Outputs
at Same Frequency
10 ps
QB[0:6] 20 ps
QC 20 ps
F
M
SSC Modulation
Frequency
Banks A, B, C 29 33.33 kHz
V
HIGH
Voltage High; NOTE 4, 5 580 1200 mV
V
LOW
Voltage Low; NOTE 4, 6 -150 mV
V
CROSS
Absolute Crossing Voltage;
NOTE 4, 7, 8
200 600 mV
ΔV
CROSS
Total Variation of V
CROSS
over all edges;
NOTE 4, 7, 9
200 mV
t
R
/ t
F
Output Rise/Fall
Time
Bank A ±150mV from crosspoint 25 100 ps
Banks B, C 20% - 80% 0.4 1.3 ns
odc Output Duty Cycle
Bank A 45 55 %
Banks B, C 42 58 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
NOTE 1: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 2: Defi ned as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDOB, C
/2.
NOTE 4: Measurement taken from single-ended waveform.
NOTE 5: Defi ned as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information
Section.
NOTE 6: Defi ned as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information
Section.
NOTE 7: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of
nQx. See Parameter Measurement Information Section.
NOTE 8: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Re-
fers to all crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 9: Defi ned as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed vari-
ance in the V
CROSS
for any particular system. See Parameter Measurement Information Section.
841S012DI Datasheet
©2016 Integrated Device Technology, Inc January 4, 20168
PARAMETER MEASUREMENT INFORMATION
HCSL OUTPUT SKEW
3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
LVCMOS OUTPUT SKEW
RMS PERIOD JITTER
LVCMOS BANK SKEW
841S012DI Datasheet
©2016 Integrated Device Technology, Inc January 4, 20169
LVCMOS RISE/FALL TIME
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
DIFFERENTIAL CYCLE-TO-CYCLE JITTER
DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD
PARAMETER MEASUREMENT INFORMATION, CONTINUED
SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT
SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS
POINT AND SWING
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME

841S012DKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner MULTIRATE FEMTOCLOCK LVPE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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