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841S012DKILF

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841S012DI Datasheet
©2016 Integrated Device Technology, Inc January 4, 201616
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 841S012DI.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 841S012DI is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Core and HCSL Output Power Dissipation
The maximum I
DD
current at 85° is 284mA. The HCSL output current (17mA per output pair) is included in this value. For power
considerations, this output current is treated separately from the core currents, so for power calculations,
I
DD
= 284mA - 2 * 17mA = 250mA.
• Power (core) = V
DD_MAX
* (I
DD
+ I
DDA
) = 3.465V * (250mA + 20mA) = 935.6mW
Power (HCSL) = 44.5mW/Load Output Pair
If all outputs are loaded, the total power is 2 * 44.5mW = 89mW
LVCMOS Output Power Dissipation
• Dynamic Power Dissipation at 200MHz, (QB, QC)
Power (200MHz) = C
PD
* Frequency * (V
DDO
)
2
= 19pF * 200MHz * (3.465V)
2
= 45mW per output
Total Power (200MHz) = 45mW * 8 = 360mW
• Dynamic Power Dissipation at 25MHz, (REF_OUT)
Power (25MHz) = C
PD
* Frequency * (V
DDO
)
2
= 19pF * 25MHz * (3.465V)
2
= 5.6mW per output
Total Power (25MHz) = 5.6mW * 2 = 11.2mW
Total Power Dissipation
• Total Power
= Power (core) + Power (HCSL) + Total Power (200MHz) + Total Power (25MHz)
= 935.6mW + 89mW + 360mW + 11mW
= 1396mW
841S012DI Datasheet
©2016 Integrated Device Technology, Inc January 4, 201617
TABLE 7. THERMAL RESISTANCE θ
JA
FOR 56 LEAD VFQFN, FORCED CONVECTION
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming 1
meter per second air fl ow and a multi-layer board, the appropriate value is 27.5°C/W per Table 7.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.396W * 27.5°C/W = 123.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (multi-layer).
θ
JA
by Velocity (Meters per second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 31.4°C/W 27.5°C/W 24.6°C/W
841S012DI Datasheet
©2016 Integrated Device Technology, Inc January 4, 201618
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 8.
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs at maximum V
DD
.
Power = (V
DD_MAX
– V
OUT
) * I
OUT,
since V
OUT
= I
OUT
* R
L
= (V
DD_MAX
– I
OUT
*
R
L
) * I
OUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 44.5mW
FIGURE 8. HCSL DRIVER CIRCUIT AND TERMINATION
V
DD
V
OUT
R
L
50
IC
I
OUT
= 17mA
R
REF
=
475
± 1%
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841S012DKILF

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Buy 841S012DKILF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner MULTIRATE FEMTOCLOCK LVPE
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