Low Capacitance, 4-/8-Channel,
±15 V/+12 V
i
CMOS Multiplexers
Data Sheet
ADG1208/ADG1209
Rev. E Document Feedback
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FEATURES
<1 pC charge injection over full signal range
1 pF off capacitance
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic compatible inputs
Rail-to-rail operation
Break-before-make switching action
Available in a 16-lead TSSOP, a 16-lead LFCSP, and a
16-lead SOIC
Typical power consumption < 0.03 µW
APPLICATIONS
Audio and video routing
Automatic test equipment
Data-acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
FUNCTIONAL BLOCK DIAGRAMS
ADG1208
S1
S8
D
ADG1209
S1A
S4B
DA
DB
S4A
S1B
1-OF-4
DECODER
1-OF-8
DECODER
A0 A1 ENA0 A1 A2 EN
05713-001
Figure 1.
GENERAL DESCRIPTION
The ADG1208 and ADG1209 are monolithic, iCMOS® analog
multiplexers comprising eight single channels and four differential
channels, respectively. The ADG1208 switches one of eight inputs
to a common output as determined by the 3-bit binary address
lines A0, A1, and A2. The ADG1209 switches one of four
differential inputs to a common differential output as determined
by the 2-bit binary address lines A0 and A1. An EN input on
both devices enable or disable the device. When disabled, all
channels are switched off. When on, each channel conducts
equally well in both directions and has an input signal range
that extends to the supplies.
The industrial CMOS (iCMOS) modular manufacturing
process combines high voltage complementary metal-oxide
semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage devices has been able to achieve. Unlike analog
ICs using conventional CMOS processes, iCMOS components
can tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Figure 2 shows that there is minimum
charge injection over the entire signal range of the device.
iCMOS construction also ensures ultralow power dissipation,
making the devices ideally suited for portable and battery-
powered instruments.
V
S
(V)
CHARGE INJECTION (pC)
1.0
0
–15 15
05713-051
0.9
0.8
0
.7
0
.6
0.5
0.4
0.3
0.2
0.1
–10
5 0 5 10
MUX (SOURCE TO DRA
IN)
T
A
= 25°C
V
DD
= +15V
V
S
S
= –15V
V
D
D
= +5V
V
SS
= –5V
V
DD
= +12V
V
SS
= 0V
Figure 2. Source to Drain Charge Injection vs. Source Voltage
ADG1208/ADG1209 Data Sheet
Rev. E | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 16
Test Circuits ..................................................................................... 17
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/2016—Rev. D to Rev. E
Changes to Analog Inputs Parameter, Table 3 .............................. 7
Added Digital Inputs Parameter, Table 3 ...................................... 7
Moved Figure 7 ............................................................................... 10
Change to Table 7 ........................................................................... 10
Deleted Table 8; Renumbered Sequentially ................................ 11
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
3/2016—Rev. C to Rev. D
Changes to Table 4 Title ................................................................... 8
Changes to Table 5 Title ................................................................... 9
Changes to Table 7 Title ................................................................. 10
Changes to Figure 7 ........................................................................ 11
Added Table 8; Renumbered Sequentially .................................. 11
Changes to Table 9 Title ................................................................. 12
8/2015—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Added Figure 4; Renumbered Sequentially .................................. 8
Changes to Table 4 ............................................................................ 8
Changes to Figure 5 .......................................................................... 9
Added Table 5; Renumbered Sequentially .................................... 9
Added Figure 7 ................................................................................ 10
Changes to Table 7 .......................................................................... 10
Changes to Figure 8 ........................................................................ 11
Added Table 8 .................................................................................. 11
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
1/2009—Rev. A to Rev. B
Change to I
DD
Parameter, Table 1 .................................................... 4
Change to I
DD
Parameter, Table 2 .................................................... 6
4/2007—Rev. 0 to Rev. A
Added 16-lead SOIC .......................................................... Universal
Changes to Table 1 ............................................................................. 3
Changes to Table 2 ............................................................................. 5
Changes to Figure 10 and Figure 11............................................. 10
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
4/2006—Revision 0: Initial Version
Data Sheet ADG1208/ADG1209
Rev. E | Page 3 of 21
SPECIFICATIONS
DUAL SUPPLY
V
DD
= +15 V ± 10%, V
SS
= 15 V ± 10%, GND = 0 V, unless otherwise noted. Temperature range is as follows: Y version: 40°C to +125°C.
Table 1.
Parameter +25ºC
40ºC to
+85ºC
40ºC to
+125ºC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
SS
to V
DD
V
On Resistance, R
ON
120 typ V
S
= ±10 V, I
S
= 1 mA, see Figure 31
200 240 270 max V
DD
= +13.5 V, V
SS
= −13.5 V
On-Resistance Match Between Channels, ∆R
ON
3.5 typ V
S
= ±10 V, I
S
= 1 mA
6 10 12 max
On-Resistance Flatness, R
FLAT
(On) 20 typ V
S
= 5 V/0 V/+5 V, I
S
= 1 mA
64
83
max
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off)
±0.003
nA typ
V
D
= ±10 V, V
S
= 10 V, see Figure 32
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, I
D
(Off) ±0.003 nA typ V
S
= 1 V/10 V, V
D
= 10 V/1 V, see Figure 32
ADG1208 ±0.1 ±0.6 ±1 nA max
ADG1209 ±0.1 ±0.6 ±1 nA max
Channel On Leakage, I
D
, I
S
(On) ±0.02 nA typ V
S
= V
D
= ±10 V, see Figure 33
ADG1208
±0.2
±1
nA max
ADG1209 ±0.2 ±0.6 ±1 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
INL
or I
INH
±0.005 µA max V
IN
= V
INL
or V
INH
±0.1 µA max
Digital Input Capacitance, C
IN
2 pF typ
DYNAMIC CHARACTERISTICS
1
Transition Time, t
TRANSITION
80 ns typ R
L
= 300 Ω, C
L
= 35 pF
130 165 185 ns max V
S
= 10 V, see Figure 34
t
ON
(EN)
75
ns typ
R
L
= 300 Ω, C
L
= 35 pF
95 105 115 ns max V
S
= 10 V, see Figure 36
t
OFF
(EN) 83 ns typ R
L
= 300 Ω, C
L
= 35 pF
100 125 140 ns max V
S
= 10 V, see Figure 36
Break-Before-Make Time Delay, t
BBM
25 ns typ R
L
= 300 Ω, C
L
= 35 pF
10 ns min V
S1
= V
S2
= 10 V, see Figure 35
Charge Injection
0.4
pC typ
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF, see Figure 37
Off Isolation −85 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 38
Channel to Channel Crosstalk −85 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
Total Harmonic Distortion Plus Noise 0.15 % typ
R
L
= 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz,
see Figure 41
−3 dB Bandwidth
550
MHz typ
R
L
= 50 Ω, C
L
= 5 pF, see Figure 39
C
S
(Off) 1 pF typ f = 1 MHz, V
S
= 0 V
1.5 pF max f = 1 MHz, V
S
= 0 V
C
D
(Off), ADG1208 6 pF typ f = 1 MHz, V
S
= 0 V
7 pF max f = 1 MHz, V
S
= 0 V
C
D
(Off), ADG1209 3.5 pF typ f = 1 MHz, V
S
= 0 V
4.5
pF max
f = 1 MHz, V
S
= 0 V

ADG1208YCPZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 8:1 550MHz 120 Ohm iCMOS
Lifecycle:
New from this manufacturer.
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