XR68C92IVTR-F Datasheet XR68C192IV-F, XR68C192CV-F, XR68C92CV-F | P10-P12

XR68C92/192

Rev. 1.33

A start-break is deferred as long as the transmitter has

characters to send, but if normal character transmis-

sion is inhibited by CTS, the start-break will proceed.

The start-break must be terminated by a stop-break or

a TX disable + TX reset before normal character

transmission can resume.

The channel A and B transmitters are enabled for data

transmission through their respective command regis-

ters (see CRA, CRB bits 3:2). The transmit FIFO

trigger levels (see MR0A, MR0B bits 4 and 5) are used

to generate an interrupt request to the CPU on the -INT

pin. This is also reflected in the Interrupt Status Regis-

ter, ISR bit-0 for channel A and bit-4 for channel B. This

is different from the TxRDY bit in the status register.

The TxRDY bit in the status register (SRA, SRB bit-2)

indicates if the TX FIFO has at least one empty

location. This can also be programmed to appear at

the output pin OP6/OP7. The TxEMT bit (SRA, SRB

bit-3) indicates if both the TX FIFO and the TX Shift

The transmitter can be reset through a software com-

mand (CRA, CRB bits 7:4). If it is reset, operation

ceases immediately and must be enabled through the

command register before resuming operation. Reset

also discards any characters in the FIFO.

RECEIVER

The channel A and B receivers are enabled for data

reception through the respective channels command

looks for the high-to-low (mark-to-space) transition of

a start bit on the receiver serial-data input pin. If

operating in 16X clock mode, the serial input data is re-

sampled on the next 7 clocks. If the receiver serial data

is sampled high, the start bit is invalid and the search

for a valid start bit begins again. If receiver serial data

is still low, a valid start bit is assumed and the receiver

continues to sample the input at one bit time intervals

(at the theoretical center of the bit) until the proper

number of data bits and the parity bit (if any) have been

assembled and one stop bit has been detected. If an 1X

clock is used, data is sampled at one bit time intervals

throughout, including the start bit. Data on the receiver

serial data input pin is sampled on the rising edge of the

programmed clock source (XTAL1, IP4 or IP6: see

CSR bits 7:4).

In this process, the least significant bit is received first.

The receiver buffer is composed of the FIFO (8/16

locations in XR68C92/192 respectively) and a receive

shift register connected to the receiver serial-data

input. Data is assembled in the shift register and

loaded into the bottom most empty FIFO location. If the

character length is less than eight bits, the most

significant unused bits are set to zero.

If the stop bit is sampled as a 1, the receiver will

immediately look for the next start bit. However, if the

stop bit is sampled as a 0, either a framing error or a

received break has occurred. If the stop bit is 0 and the

data and parity (if any) are not all zero, it is a framing

error. The damaged character is transferred to the

FIFO with the framing error flag set. If the receiver

serial data remains low for one-half of the bit period

after the stop bit was sampled, the receiver operates as

if a new start bit transition has been detected. If the stop

bit is 0 and the data and parity (if any) bits are also all

zero, it is a break. A character consisting of all zeros will

be loaded into the the FIFO with the received-break bit

(but not the framing error bit) set to one. The receiver

serial-data input must return to a high condition for at

least one-half bit time before a search for the next start

bit begins. Also, at this time, the received break bit is

reset.

The receiver can detect a break that starts in the middle

of a character provided the break persists completely

through the next character time or longer. When the

break begins in the middle of a character, the receiver

will place the damaged character in the FIFO with the

framing error bit set. Then, provided the break persists

through the next character time, the receiver will also

place an all-zero character in the FIFO with the re-

ceived-break bit set. The parity error, framing error,

overrun error, and received-break conditions (if any)

set error and break flags in the status register at the

received character boundary and are valid only when

the receiver-ready bit (RXRDY) in the status register is

set.

The receiver-ready bit in the status register (SRA, SRB

bit-0) is set whenever one or more characters are

available to be read by the CPU. A read of the receiver

buffer produces an output of data from the top of the

FIFO stack. After the read cycle, the data at the top of

the FIFO stack and its associated status bits are

“popped” and new data can be added at the bottom of

the stack by the receive shift register. The FIFO-full

status bit (SRA, SRB bit-1) is set if all 8 (or 16) stack

positions are filled with data. Either the receiver-ready

XR68C92/192

Rev. 1.33

or the FIFO-full status bits can be selected to cause an

interrupt (see MR1A, MR1B bit-6).

In addition to the data byte, three status bits (parity

error, framing error, and received break) are appended

to each data character in the FIFO (overrun is not). By

programming the error-mode control bit (MR1A, MR1B

bit-5), status can be provided for “character” or “block”

modes. In the “character” mode, the status register

(SRA, SRB) is updated on a character-by-character

basis and applies only to the character at the top of the

FIFO. Thus, the status must be read before the char-

acter is read. Reading the character pops the data byte

and its error flags off the FIFO. In the “block” mode, the

status provided in the status register for the parity error,

framing error, and received-break conditions are the

logical OR of these respective bits, for all the data bytes

in the FIFO stack since the last reset error command

(see CRA, CRB bits 7:4) was issued. That is, beginning

immediately after the last reset-error command was

issued, a continuous logical-OR function of corre-

sponding status bits is produced in the status register

as each character enters the FIFO.

The block mode is useful in applications requiring the

exchange of blocks of information where the software

overhead of checking each character's error flags

cannot be tolerated. In this mode, entire messages can

be received and only one data integrity check is per-

formed at the end of each message. Although data

reception in this manner has speed advantages, there

are also disadvantages. If an error occurs within a

message the error will not be recognized until the final

check is performed. Also, there is no indication of

which character(s) is in error within the message.

Reading the status register (SRA, SRB) does not affect

the FIFO. The FIFO is “popped” only when the receive

buffer is read. If the FIFO is full when a new character

is received, that character is held in the receive shift

tional character is received while this state exists, the

contents of the FIFO are not affected, but the character

previously in the shift register is lost and the overrun-

error status bit will be set upon receipt of the start bit of

the new overrunning character.

To support flow control, a receiver can automatically

negate and reassert the request-to-send (RTS) output

(RX RTS control - see MR1A, MR1B bit-7). The re-

quest-to-send output (at OP0 or OP1 for channel A or

B respectively) will automatically be negated by the

receiver when a valid start bit is received and the FIFO

stack is full. When a FIFO position becomes available,

the request-to-send output will be reasserted auto-

matically by the receiver. Connecting the request-to-

send output to the clear-to send (CTS) input of a

transmitting device prevents overrun errors in the

receiver. The RTS output must be manually asserted

the first time. Thereafter, the receiver will control the

RTS output.

If the FIFO stack contains characters and the receiver

is then disabled, the characters in the stack can still be

read but no additional characters can be received until

the receiver is again enabled. If the receiver is disabled

while receiving a character, or while there is a charac-

ter in the shift register waiting for a FIFO opening, these

characters are lost. If the receiver is reset, the FIFO

stack and all of the receiver status bits, the correspond-

ing output ports, and the interrupt request are reset. No

additional characters can be received until the receiver

is again enabled.

LOOPBACK MODES

Besides the normal operation mode in which the re-

ceiver and transmitter operate independently, each

XR68C92/192 channel can be configured to operate in

various looping modes (see MR2A, MR2B bits 7:6) that

are useful for local and remote system diagnostic

functions.

AUTOMATIC ECHO MODE

In this mode, the channel automatically retransmits the

received data on a bit-by-bit basis. The local CPU-to-

receiver communication continues normally but the

CPU-to-transmitter link is disabled.

LOCAL LOOPBACK MODE

In this mode, the transmitter output is internally con-

nected to the receiver input. The external TX pin is held

in the mark (high) state in this mode. By sending data

to the transmitter and checking that the data as-

sembled by the receiver is the same data that was sent,

proper channel operation can be assured. In this mode

the CPU-to-transmitter and CPU-to-receiver commu-

nications continue normally.

REMOTE LOOPBACK MODE

In this mode, the channel automatically retransmits the

received data on a bit-by-bit basis. The local CPU-to-

receiver and CPU-to-transmitter links are disabled.

XR68C92/192

Rev. 1.33

This mode is useful in testing the receiver and transmit-

ter operation of a remote channel. This mode requires

the remote channel receiver to be enabled.

MULTIDROP MODE - Enhanced with Extra A/D Tag

Storage

Users can program the channel to operate in a wake-

up mode for Multidrop applications. In this mode of

operation (set MR1A, MR1B bits 4:3 = 11), the

XR68C92/192, as a master station channel connected

to several slave stations (a maximum of 256 unique

slave stations), transmits an address character fol-

lowed by a block of data characters targeted for one or

more of the slave stations. The channel receivers

within the slave stations are disabled, but they continu-

ously monitor the data stream sent out from the master

station. When the slave stations' receivers detect an

address character, each receiver notifies its respective

CPU by setting receiver ready (-RXRDY) and generat-

ing an interrupt, if programmed to do so. Each slave

station CPU then compares the received address to its

station address and enables its receiver if the ad-

dresses match. Slave stations that are not addressed,

continue monitoring the data stream for the next ad-

dress character. An address character marks the

beginning of a new block of data. After receiving a block

of data, the slave stations CPU may disable the chan-

nel receiver and re-initiate the process.

A transmitted character from the master station con-

sists of a start bit, the programmed number of data bits,

an address/data (A/D) bit tag (replacing the parity bit

used in normal operation), and the programmed num-

ber of stop bits. The A/D tag indicates to the slave

stations channel whether the character should be

interpreted as an address character or a data charac-

ter. The character is interpreted as an address charac-

ter if the A/D tag is set to a '1' or interpreted as a data

character if it is set to a '0'. The polarity of the transmit-

ted A/D tag is selected by programming MR1A, MR1B

bit-2 to a '1' for an address character and to a '0' for data

characters. Users should program the mode register

prior to loading the corresponding data or address

characters into the transmit buffer.

As a slave station, the XR68C92/192 receiver continu-

ously monitors the received data stream regardless of

whether it is enabled or disabled. If the receiver is

disabled, it sets the receiver ready status bit and loads

the character into the FIFO receive holding register

stack provided the received A/D tag is a '1' (address

tag). The received character is discarded if the received

address/data bit is a '0' (data tag). If the receiver is

enabled, all received characters are transferred to the

CPU during read operations. In either case, the data

bits are loaded into the data portion of the FIFO stack

while the address/data bit is loaded into the status

portion of the FIFO stack normally used for parity error

(SRA, SRB bit-5). Framing error, overrun error, and

break-detection operate normally regardless of whether

the receiver is enabled or disabled. The address/data

(A/D) tag takes the place of the parity bit and parity is

neither calculated nor checked for characters in this

mode.

Extra Storage For The A/D Tag: The unique feature of

XR68C92/192 is that the the user need not wait at all in

order to change the A/D tag from address to data

(whereas in the case of SC26C92, a wait of at least 2

bit-times is required before changing the A/D tag). This

allows the user to possibly load the entire polling packet

data to the TX FIFO.

WATCHDOG TIMER

Each of the two receivers (channel A & B) has its own

'watchdog timer' which is separate from and indepen-

dent of the Counter/Timer. The watchdog timer is used

to generate a receive ready time-out interrupt. When it

is enabled, a counter is started everytime a character

is transferred from the receive shift register to the

receive FIFO and times out after 64 bit-times, at which

point it will generate a receive interrupt. This is a useful

feature especially when the incoming data is not a

continous stream of data. For example, if RX trigger

levels are used and the last set of characters is smaller

than the trigger level, a receive time-out interrupt is

generated instead of a regular receive interrupt. The

watchdog timer, however, is not accurate as it uses the

incoming data for its timing. For more accurate timing,

the time-out mode in Counter/Timer should be used

(see below).

COUNTER/TIMER

The 16-bit counter/timer (C/T) can operate in a counter

mode or a timer mode. In either mode, users can

program the C/T input clock source to come from

several sources (see ACR bits 6:4) and program the

C/T output to appear on output port pin OP3 (see

OPCR bits 3:2). The value (pre-load value) stored in

the concatenation of the C/T upper register (CTPU,

address 0x6) and the C/T lower register (CTPL, ad-

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

XR68C92IVTR-F

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UART Interface IC XR68C92IVTR-F

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