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XR68C92IVTR-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
XR68C92/192
4
Rev. 1.33
SYMBOL DESCRIPTION (* 44 pin LQFP)
-RESET 38 34 32 I Master Reset (active low). A low on this pin will reset all the
outputs and internal registers. The transmitter output and
the receiver input will be disabled during reset time.
A0-A3 2,4, 1,3, 40,42,
6,7 5,6 44,1 I Address select lines. To select internal registers.
-IACK 41 37 35 I Interrupt acknowledge (active low). A low on this pin indicates
that the CPU has received an interrupt. If not used, this pin
should be tied to VCC.
-DACK 10 9 4 O Data Transfer Acknowledge ( three-state active low output).
A low on this pin indicates proper transfer of data between
the CPU and XR68C92/192 during read, write and interrupt
cycles.
-CS 39 35 33 I Chip select (active low). A low at this pin enables the data
bus transfer operation.
D0-D7 28,18 25,16 22,12 Bi-directional data bus. Eight bit, three state data bus to
27,19 24,17 21,13 I/O transfer information to or from the CPU. D0 is the least
26,20 23,18 20,14 significant bit of the data bus and the first serial data bit to be
25,21 22,19 19,15 received or transmitted.
R/-W 9 8 3 I Read/Write strobe. When -CS is asserted, a high on this pin
transfers the contents of the XR68C92/192 data bus to the
CPU, and a low on this pin will transfer the contents of the
CPU data bus to the addressed register.
-INT 24 21 18 O Interrupt output (open drain, active low) This pin goes low
upon occurrence of one or more of eight maskable interrupt
conditions (when enabled by the interrupt mask register).
CPU can read the interrupt status register to determine the
interrupting condition(s). This output requires a 10k ohms
pull-up resistor.
XTAL1 36 32 30 I Crystal input 1 or external clock input. A crystal can be
connected between this pin and XTAL2 pin to utilize the
internal oscillator circuit. An external clock can be used to
clock internal circuit and baud rate generator for custom
transmission rates.
Symbol Pin Signal Pin Description
44 40 44* type
XR68C92/192
5
Rev. 1.33
SYMBOL DESCRIPTION (* 44 pin LQFP)
XTAL2 37 33 31 O Crystal input 2 or buffered clock output. See XTAL1.
RXA, RXB 35,11 31,10 29,5 I Serial data input. The serial information (data) received from
serial port to XR68C92/192 receive input circuit. A mark
(high) is logic one and a space (low) is logic zero.This input
must be held at logic one when idle and during power down.
TXA, TXB 33,13 30,11 28,6 O Serial data output. The serial data is transmitted via this pin
with additional start , stop and parity bits. This output will be
held in mark (high) state during reset, local loop back mode
or when the transmitter is disabled.
IP0 8 7 2 I Multi-purpose input or Channel A Clear-To-Send (-CTSA
active low). If not used, this pin should be tied to VCC.
IP1 5 4 43 I Multi-purpose input or Channel B Clear-To-Send (-CTSB
active low). If not used, this pin should be tied to VCC.
IP2 40 36 34 I Multi-purpose input or Channel B receive external clock
input (received data is sampled on the rising edge of the
clock) or Timer/Counter External clock input. If not used, this
pin should be tied to VCC or GND.
IP3 3 2 41 I Multi-purpose input or Channel A transmit external clock
input. The transmit data is clocked on the falling edge of the
clock. If not used, this pin should be tied to VCC or GND.
IP4 43 39 37 I Multi-purpose input or Channel A receive external clock
input. The received data is clocked on the rising edge of the
clock. If not used, this pin should be tied to VCC or GND.
IP5 42 38 36 I Multi-purpose input or Channel B transmit external clock
input. The transmit data is clocked on the falling edge of the
clock. If not used, this pin should be tied to VCC or GND.
OP0 32 29 27 O Multi-purpose output. General purpose output or Channel A
Request-To-Send (-RTSA active low).
OP1 14 12 7 O Multi-purpose output. General purpose output or Channel B
Request-To-Send (-RTSB active low).
OP2 31 28 26 O Multi-purpose output. General purpose output or one of the
Symbol Pin Signal Pin Description
44 40 44* type
XR68C92/192
6
Rev. 1.33
SYMBOL DESCRIPTION (* 44 pin LQFP)
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bits 1,0;
TxAClk1 -Transmit 1X clock.
TxAClk16 -Transmit 16X clock
RxAClk1 -Receive 1X clock
OP3 15 13 8 O Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bits 3,2;
C/T -Counter timer output (Open drain output)
TxBClk1 -Transmit 1X clock
RxBClk1 -Receive 1X clock
OP4 30 27 25 O Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bit 4;
-RxARDY -Receive ready signal (Open drain output)
-RxAFULL - Receive FIFO full signal (Open drain output)
OP5 16 14 9 O Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bit 5;
-RxBRDY - Receive ready signal (Open drain output)
-RxBFULL - Receive FIFO full signal (Open drain output)
OP6 29 26 24 O Multi-purpose output. General purpose output or Transmit A
holding register empty interrupt (-TxARDY Open drain out-
put).
OP7 17 15 10 O Multi-purpose output. General purpose output or Transmit B
holding register empty interrupt (-TxBRDY Open drain out-
put)
GND 22 20 16,17 Pwr Signal and power ground.
VCC 44 40 38,39 Pwr Power supply input, 2.97V to 5.5V.
N.C. 1,12 - 11,23 No Connection.
23,34
Symbol Pin Signal Pin Description
44 40 44* type
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

XR68C92IVTR-F

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Buy XR68C92IVTR-F
Manufacturer:
MaxLinear
Description:
UART Interface IC XR68C92IVTR-F
Lifecycle:
New from this manufacturer.
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