XR68C92IVTR-F

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

XR68C92/192

28

Rev. 1.33

ExCLK

XR92-CK

T1w T2w

T3w

Figure 6: External clock Timing

Figure 5: Output Port Timing

Figure 7: Interrupt Timing

-IACK

Interrupt Vector

-INT

D7-D0

-DACK

T

AKL

T

DD

T

DF

T

AKH

T

AK T

Hi-Z

Figure 4: Input Port Timing

T9s T9h

IP6-IP0

XR92-IP

-CS

T10d

OP7-OP0

XR92-OP

-CS

Old Data New Data

XR68C92/192

29

Rev. 1.33

Figure 8: Receive Timing

Figure 9: Transmit Timing

XR92-RX

D1 D2 D8 D9 D10 D11 D12 D13

RX

RX

ENABLE

-RxRDY

-FFULL

-RxRDY/

-FFULL

-CS

(Read)

OVERRUN

ERROR

-RTS

Status Data

(D1)

Status Data

(D2)

Status Data

(D3)

Status Data

(D10)

D11 Will be lost

due to overrun

Reset by

command

D12, D13 Will be lost

due to RX disable

XR692-TX

D1 D2 D3 D4

Break

D5

TX

TX

ENABLE

-TxRDY

-CS

(Write)

-CTS

-RTS

XR68C92/192

30

Rev. 1.33

40

1

21

20

D

e

A

1

E

1

A

L

Seating

Plane

A

2

B

1

B

PACKAGE OUTLINE DRAWING

40 LEAD PLASTIC DUAL-IN-LINE

(PDIP)

SYMBOL

MIN MAX MIN MAX

INCHES MILLIMETERS

A

α

L

e

B

e

A

e

E

1

E

D

C

B

1

B

A

2

A

1

6.35

15

0

5.08

17.78

14.73

15.88

53.21

0.38

1.78

0.56

4.95

1.78

4.06

0

0

2.92

15.24

15.24 BSC

2.54 BSC

12.32

15.24

50.29

0.20

0.76

0.36

3.18

0.38

0.250

15

0

0.200

0.700

0.580

0.625

2.095

0.014

0.070

0.024

0.195

0.070

0.160

0

0

0.115

0.600

0.600 BSC

0.100 BSC

0.485

0.600

1.980

0.008

0.030

0.014

0.125

0.015

Note: The control dimension is the inch column

E

α

C

e

B

e

A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

XR68C92IVTR-F

Mfr. #:

Buy XR68C92IVTR-F

Manufacturer:

MaxLinear

Description:

UART Interface IC XR68C92IVTR-F

Lifecycle:

New from this manufacturer.

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