XR68C92/192
14
Rev. 1.33
command register) and the CPU cannot stop it. When
the stop command is issued (by reading the stop C/T
command register), the CPU only resets the C/T inter-
rupt. This mode allows the C/T to be used as a
programmable clock source for channels A and B (see
CSRA, CSRB register), and/or a periodic interrupt
generator. In this mode, the C/T generates a square-
wave output (see Figure 2) derived from the pro-
grammed timer input clock source. The square wave
generated by the timer has a period of 2 X (pre-load
value) X (period of clock source) and is available as a
clock source for both channels A and B. Since the timer
cannot be stopped, the values in the registers
(CUR:CLR) should not be read. See description of
ACR register to see how to choose clock source for the
C/T.
When the start counter command register (STCR,
address 0xE) is read, the C/T terminates the current
countdown sequence and sets its output to a '1' (OP3
can be programmed to show this output). The C/T is
then initialized to the pre-load value, and begins a new
countdown sequence. When the terminal count is
reached (0x0000), the C/T sets its output to a '0'. Then,
it gets re-initialized to the pre-load value and repeats
the countdown sequence. See Figure 2 for the result-
ing waveform.
The timer sets the C/T-ready bit in the interrupt status
register (ISR Bit-3) every other time it reaches the
terminal count (at every rising edge of the output).
Users can program the timer to generate an interrupt
request for this condition (every second countdown
cycle) on the -INT output. If the CPU changes the pre-
load value, the timer will not recognize the new value
until either
(a) it reaches the next terminal count and is reinitialized
automatically, or
(b) it is forced to re-initialize by a start command.
When a read at the stop counter command address is
performed, the timer clears ISR Bit-3 but does not stop.
Because in timer mode the C/T runs continuously, it
should be completely configured (pre-load value
loaded and start counter command issued) before
programming the timer output to appear on OP3.
OTHER PROGRAMMING REMARKS
The contents of internal registers should not be
changed during receiver/transmitter operation as cer-
tain changes can produce undesired results. For ex-
ample, changing the number of bits per character while
the transmitter is active will result in transmitting an
incorrect character. The contents of the clock-select
register (CSR) and ACR Bit-7 should only be changed
after the receiver(s) and transmitter(s) have been
issued software RX and TX reset commands. Simi-
larly, changes to the auxiliary control register (ACR Bits
4-6) should only be made while the counter/timer (C/T)
is not used.
The mode registers of each channel MR0, MR1 and
MR2 are accessed via an auxiliary pointer. The pointer
is set to mode register one (MR1) by RESET. It can be
set to MR0 or MR1 by issuing a “reset pointer”
command (0xB0 or 0x10 respectively) via the
channel's command register. Any read or write of the
mode register switches the pointer to next mode reg-
ister. All accesses subsequent to reading/writing MR1
will address MR2 unless the pointer is reset to MR0 or
MR1 as described above. The mode, command,
clock-select, and status registers are duplicated for
each channel to allow independent operation and
control (except that both channels are restricted to
baud rates that are in the same set).
