MAX1304ECM+ Datasheet MAX1304ECM+, MAX1314ECM+, MAX1309ECM+ | P13-P15

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

______________________________________________________________________________________ 13

Pin Description

MAX1304

MAX1308

MAX1312

MAX1305

MAX1309

MAX1313

MAX1306

MAX1310

MAX1314

NAME

FUNCTION

1, 15, 17 1, 15, 17 1, 15, 17 AVDD

Analog Power Input. AVDD is the power input for the analog section of the

converter. Apply +5V to AVDD. Connect all AVDD pins together. See the

Layout, Grounding, and Bypassing section for additional information.

2, 3, 14,

16, 23

2, 3, 14,

16, 23

2, 3, 14,

16, 23

AGND

Analog Ground. AGND is the power return for AVDD. Connect all AGND

pins together.

4 4 4 CH0 Channel 0 Analog Input

5 5 5 CH1 Channel 1 Analog Input

666MSV

Midscale Voltage Bypass. For the unipolar MAX1304/MAX1305/MAX1306,

connect a 2.2µF and a 0.1µF capacitor from MSV to AGND. For the bipolar

MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314, connect

MSV to AGND.

7 7 — CH2 Channel 2 Analog Input

8 8 — CH3 Channel 3 Analog Input

9 — — CH4 Channel 4 Analog Input

10 — — CH5 Channel 5 Analog Input

11 — — CH6 Channel 6 Analog Input

12 — — CH7 Channel 7 Analog Input

13 13 13

INTCLK/

EXTCLK

Clock-Mode Select Input. Connect INTCLK/EXTCLK to AVDD to select the

internal clock. Connect INTCLK/EXTCLK to AGND to use an external clock

connected to CLK.

18 18 18

REF

Midscale Reference Bypass or Input. REF

connects through a 5k_ resistor to

the internal +2.5V bandgap reference buffer.

For the MAX1304/MAX1305/MAX1306 unipolar devices, V

REFMS

is the input to

the unity-gain buffer that drives MSV. MSV sets the midpoint of the input voltage

range. For internal reference operation, bypass REF

with a ≥ 0.01µF

capacitor to AGND. For external reference operation, drive REF

with an

external voltage from +2V to +3V.

For the MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314 bipolar

devices, connect REF

to REF. For internal reference operation, bypass the

REF

/REF node with a ≥ 0.01µF capacitor to AGND. For external reference

op er ati on, d r i ve the RE F

M S

/RE F nod e w i th an exter nal vol tag e fr om + 2V to + 3V .

19 19 19 REF

ADC Reference Bypass or Input. REF connects through a 5k_ resistor to the

internal +2.5V bandgap reference buffer.

For internal reference operation, bypass REF with a ≥ 0.01µF capacitor.

For external reference operation with the MAX1304/MAX1305/MAX1306

unipolar devices, drive REF with an external voltage from +2V to +3V.

For external reference operation with the MAX1308/MAX1309/MAX1310/

MAX1312/MAX1313/MAX1314 bipolar devices, connect REF

to REF and

drive the REF

/REF node with an external voltage from +2V to +3V.

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

14 ______________________________________________________________________________________

Pin Description (continued)

MAX1304

MAX1308

MAX1312

MAX1305

MAX1309

MAX1313

MAX1306

MAX1310

MAX1314

NAME

FUNCTION

20 20 20

REF+

Positive Reference Bypass. Bypass REF+ with a 0.1µF capacitor to AGND. Also

bypass REF+ to REF- with a 2.2µF and a 0.1µF capacitor.

REF+

= V

COM

+ V

REF

/2.

21 21 21

COM

Reference Common Bypass. Bypass COM to AGND with a 2.2µF and a 0.1µF

capacitor. V

COM

= 13/25 x AVDD.

22 22 22

REF-

Negative Reference Bypass. Bypass REF- with a 0.1µF capacitor to AGND.

Also bypass REF- to REF+ with a 2.2µF and a 0.1µF capacitor.

REF-

= V

COM

- V

REF

/2.

24, 39 24, 39 24, 39

DGND

Digital Ground. DGND is the power return for DVDD. Connect all DGND

pins together.

25, 38 25, 38 25, 38

DVDD

Digital Power Input. DVDD powers the digital section of the converter, including

the parallel interface. Apply +2.7V to +5.25V to DVDD. Bypass DVDD to DGND

with a 0.1µF capacitor. Connect all DVDD pins together.

26 26 26 D0 D i g i tal I/O 0 of 12- Bi t P ar al l el D ata Bus. H i g h i m p ed ance w hen RD = 1 or CS = 1.

27 27 27 D1 D i g i tal I/O 1 of 12- Bi t P ar al l el D ata Bus. H i g h i m p ed ance w hen RD = 1 or CS = 1.

28 28 28 D2 D i g i tal I/O 2 of 12- Bi t P ar al l el D ata Bus. H i g h i m p ed ance w hen RD = 1 or CS = 1.

29 29 29 D3 D i g i tal I/O 3 of 12- Bi t P ar al l el D ata Bus. H i g h i m p ed ance w hen RD = 1 or CS = 1.

30 30 30 D4 D i g i tal I/O 4 of 12- Bi t P ar al l el D ata Bus. H i g h i m p ed ance w hen RD = 1 or CS = 1.

31 31 31 D5 D i g i tal I/O 5 of 12- Bi t P ar al l el D ata Bus. H i g h i m p ed ance w hen RD = 1 or CS = 1.

32 32 32 D6 D i g i tal I/O 6 of 12- Bi t P ar al l el D ata Bus. H i g h i m p ed ance w hen RD = 1 or CS = 1.

33 33 33 D7 D i g i tal I/O 7 of 12- Bi t P ar al l el D ata Bus. H i g h i m p ed ance w hen RD = 1 or CS = 1.

34 34 34 D8

Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or

CS = 1.

35 35 35 D9

Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or

CS = 1.

36 36 36 D10

Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or

CS = 1.

37 37 37 D11

Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or

CS = 1.

40 40 40 EOC

E nd - of- C onver si on Output. EOC goes low to i nd i cate the end of a conver si on. It

r etur ns hi g h on the next r i si ng C LK ed g e or the fal l i ng C ON V S T ed g e.

41 41 41

EOLC

End-of-Last-Conversion Output. EOLC goes low to indicate the end of the

last conversion. It returns high when CONVST goes low for the next

conversion sequence.

42 42 42 RD Read Inp ut. P ul l i ng RD l ow i ni ti ates a r ead com m and of the p ar al l el d ata b us.

43 43 43 WR

Write Input. Pulling WR low initiates a write command for configuring the device

with D0–D7.

MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

______________________________________________________________________________________ 15

Detailed Description

The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–

MAX1314 are 12-bit ADCs. The devices offer 8, 4, or 2

independently selectable input channels, each with

dedicated T/H circuitry. Simultaneous sampling of all

active channels preserves relative phase information

making these devices ideal for motor control and power

monitoring. Three input ranges are available, 0 to +5V,

±5V and ±10V. The 0 to +5V devices provide ±6V fault-

tolerant inputs. The ±5V and ±10V devices provide

±16.5V fault-tolerant inputs. Two-channel conversion

results are available in 0.9µs. Conversion results from

all eight channels are available in 1.98µs. The 8-chan-

nel throughput is 456ksps per channel. Internal or

external reference and clock capability offer great flexi-

bility, and ease of use. A write-only configuration regis-

ter can mask out unused channels and a shutdown

feature reduces power. A 20MHz, 12-bit, parallel data

bus outputs the conversion results. Figure 2 shows the

functional diagram of these ADCs.

100pF

DEVICE PIN

= 1.6mA

= 0.8mA

1.6V

Figure 1. Digital Load Test Circuit

Pin Description (continued)

MAX1304

MAX1308

MAX1312

MAX1305

MAX1309

MAX1313

MAX1306

MAX1310

MAX1314

NAME

FUNCTION

44 44 44 CS

Chip-Select Input. Pulling CS low activates the digital interface. Forcing CS high

places D0–D11 in high-impedance mode.

45 45 45

C ON V S T

Conversion Start Input. Driving CONVST high initiates the conversion process.

The analog inputs are sampled on the rising edge of CONVST.

46 46 46 CLK

External Clock Input. For external clock operation, connect INTCLK/EXTCLK to

AGND and drive CLK with an external clock signal from 100kHz to 20MHz. For

internal clock operation, connect INTCLK/EXTCLK to AVDD and connect CLK

to DGND.

47 47 47

SHDN

Shutdown Input. Driving SHDN high initiates device shutdown. Connect SHDN

to DGND for normal operation.

48 48 48

CHSHDN

Active-Low Analog-Input Channel-Shutdown Input. Drive CHSHDN low to

power down analog inputs that are not selected for conversion in the

configuration register. Drive CHSHDN high to power up all analog input

channels regardless of whether they are selected for conversion in the

configuration register. See the Channel Shutdown (

CHSHDN

) section for more

information.

—

9, 10,

11, 12

7, 8, 9,

10, 11, 12

I.C. Internally connected. Connect I.C. to AGND.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

MAX1304ECM+

Mfr. #:

Buy MAX1304ECM+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 12-Bit 8Ch 1.075Msps 3V Precision ADC

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New from this manufacturer.

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MAX1304ECM+

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