MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________ 19
Analog Inputs
Track and Hold (T/H)
To preserve phase information across the multichannel
MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314, all input channels have dedicated T/H ampli-
fiers. Figure 5 shows the equivalent analog input T/H
circuit for one channel.
The input T/H circuit is controlled by the CONVST input.
When CONVST is low, the T/H circuit tracks the analog
input. When CONVST is high the T/H circuit holds the
analog input. The rising edge of CONVST is the analog
input sampling instant. There is an aperture delay (t
AD
)
of 8ns and a 50ps
RMS
aperture jitter (t
AJ
). The aperture
delay of each dedicated T/H input is matched within
100ps of each other.
To settle the charge on C
SAMPLE
to 12-bit accuracy,
use a minimum acquisition time (t
ACQ
) of 100ns.
Therefore, CONVST must be low for at least 100ns.
Although longer acquisition times allow the analog input
to settle to its final value more accurately, the maximum
acquisition time must be limited to 1ms. Accuracy with
conversion times longer than 1ms cannot be guaran-
teed due to capacitor droop in the input circuitry.
Due to the analog input resistive divider formed by R1
and R2 in Figure 5, any significant analog input source
resistance (R
SOURCE
) results in gain error. Further-
more, R
SOURCE
causes distortion due to nonlinear
analog input currents. Limit R
SOURCE
to a maximum
of 100.
Selecting an Input Buffer
To improve the input signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance (15pF) and
settle quickly. For example, the MAX4431 or the
MAX4265 can be used for the 0 to +5V unipolar devices,
or the MAX4350 can be used for ±5V bipolar inputs.
Most applications require an input buffer to achieve 12-bit
accuracy. Although slew rate and bandwidth are impor-
tant, the most critical input buffer specification is settling
time. The simultaneous sampling of multiple channels
requires an acquisition time of 100ns. At the beginning of
the acquisition, the ADC internal sampling capacitor array
connects to the analog inputs, causing some distur-
bance. Ensure the amplifier is capable of settling to at
least 12-bit accuracy during this interval. Use a low-noise,
low-distortion, wideband amplifier that settles quickly and
is stable with the ADC’s 15pF input capacitance.
See the Maxim website at www.maxim-ic.com
for
application notes on how to choose the optimum buffer
amplifier for your ADC application.
Input Bandwidth
The input-tracking circuitry has a 20MHz small-signal
bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Input Range and Protection
The MAX1304/MAX1305/MAX1306 provide a 0 to +5V
input voltage range with fault protection of ±6V. The
MAX1308/MAX1309/MAX1310 provide a ±5V input volt-
age range with fault protection of ±16.5V. The
MAX1312/MAX1313/MAX1314 provide a ±10V input
voltage range with fault protection of ±16.5V. Figure 5
shows the single-channel equivalent input circuit.
CH_
UNDERVOLTAGE
PROTECTION
CLAMP
OVERVOLTAGE
PROTECTION
CLAMP
R1
2.5pF
AV
DD
C
SAMPLE
C
HOLD
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
R1 | | R2 = 2k
R2
V
BIAS
*R
SOURCE
ANALOG
SIGNAL
SOURCE
*MINIMIZE R
SOURCE
TO AVOID GAIN ERROR AND DISTORTION.
INPUT RANGE (V)PART
0 TO +5
MAX1304
MAX1305
MAX1306
MAX1308
MAX1309
MAX1310
MAX1312
MAX1313
MAX1314
±5
±10
R1 (k
)
3.33
6.67
13.33
R2 (k
) V
BIAS
(V)
5.00
2.86
2.35
0.90
2.50
2.06
Figure 5. Single-Channel, Equivalent Analog Input T/H Circuit
MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
20 ______________________________________________________________________________________
Data Throughput
The data throughput (f
TH
) of the MAX1304–MAX1306/
MAX1308–MAX1310/MAX1312–MAX1314 is a function
of the clock speed (f
CLK
). In internal clock mode, f
CLK
=
15MHz (typ). In external clock mode, 100kHz f
CLK
20MHz. When reading during conversion (Figures 7 and
8), calculate f
TH
as follows:
where N is the number of active channels and t
QUIET
is
the period of bus inactivity before the rising edge of
CONVST. See the
Starting a Conversion
section for
more information.
Table 1 uses the above equation and shows the total
throughput as a function of the number of channels
selected for conversion.
Clock Modes
The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 provide a 15MHz internal conversion clock.
Alternatively, an external clock can be used.
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For inter-
nal clock operation, connect INTCLK/EXTCLK to AVDD
and connect CLK to DGND. Note that INTCLK/EXTCLK
is referenced to AV
DD
, not DV
DD
.
External Clock
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to AVDD, not
DVDD. The external clock frequency can be up to
20MHz. Linearity is not guaranteed with clock frequen-
cies below 100kHz due to droop in the T/H circuits.
f
tt
xN
f
TH
ACQ QUIET
CLK
=
++
+−+
1
12 3 1 1()
Table 1. Throughput vs. Channels Sampled: f
CLK
= 15MHz, t
ACQ
= 100ns, t
QUIET
= 50ns
CHANNELS
SAMPLED
(N)
CLOCK CYCLES
UNTIL
LAST RESULT
CLOCK CYCLE
FOR READING
LAST CONVERSION
TOTAL
CONVERSION
TIME (ns)
TOTAL
THROUGHPUT
(ksps)
THROUGHPUT
PER CHANNEL
(f
TH
)
1 12 1 800 983 983
2 15 1 1000 1643 821
3 18 1 1200 2117 705
4 21 1 1400 2474 618
5 24 1 1600 2752 550
6 27 1 1800 2975 495
7 30 1 2000 3157 451
8 33 1 2200 3310 413
MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________ 21
Applications Information
Digital Interface
The bidirectional parallel digital interface allows for setting
the 8-bit configuration register (see the
Configuration
Register
section) and reading the 12-bit conversion
result. The interface includes the following control signals:
chip select (CS), read (RD), write (WR), end of conversion
(EOC), end of last conversion (EOLC), conversion start
(CONVST), shutdown (SHDN), channel shutdown
(CHSHDN), internal clock select (INTCLK/EXTCLK), and
external clock input (CLK). Figures 6, 7, 8, 9, Table 2, and
the
Timing Characteristics
show the operation of the inter-
face. D0–D7 are bidirectional, and D8–D11 are output
only. D0–D11 go high impedance when RD = 1 or CS = 1.
Configuration Register
Enable channels as active by writing to the configura-
tion register through I/O lines D0–D7 (Table 2). The bits
in the configuration register map directly to the chan-
nels, with D0 controlling channel zero, and D7 control-
ling channel seven. Setting any bit high activates the
corresponding input channel, while resetting any bit
low deactivates the corresponding channel. On the
devices with less than eight channels, some of the bits
have no function (Table 2).
To write to the configuration register, pull CS and WR
low, load bits D0 through D7 onto the parallel bus, and
force WR high. The data are latched on the rising edge
of WR (Figure 6). Write to the configuration register at
any point during the conversion sequence. At power-
up, write to the configuration register to select the
active channels before beginning a conversion.
However, the new configuration does not take effect
until the next CONVST falling edge. At power-up all
channels default active. Shutdown does not change the
configuration register. The configuration register may
be written to in shutdown. See the
Channel Shutdown
(
CHSHDN
)
section for information about using the con-
figuration register for power saving.
Table 2. Configuration Register
BIT/CHANNEL
PART
NUMBER
STATE
D0/CH0 D1/CH1 D2/CH2 D3/CH3 D4/CH4 D5/CH5 D6/CH6 D7/CH7
ON11111111
MAX1304
MAX1308
MAX1312
OFF00000000
ON1111XXXX
MAX1305
MAX1309
MAX1313
OFF0000XXXX
ON 11XXXXXX
MAX1306
MAX1310
MAX1314
OFF00XXXXXX
X = Don’t care (must be 1 or 0).
D0–D7
DATA-IN
RD
CONVST
CONFIGURATION
REGISTER UPDATES
CS
WR
t
CS
t
WRL
t
CTW
t
DTW
t
WTD
t
WTC
Figure 6. Write Timing

MAX1304ECM+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 8Ch 1.075Msps 3V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union