MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EXTERNAL REFERENCE (REF and REF
MS
are externally driven)
REF Input Voltage Range V
REF
2.0 2.5 3.0 V
REF Input Resistance R
REF
(Note 5) 5 k
REF Input Capacitance 15 pF
REF
MS
Input Voltage Range V
REFMS
2.0 2.5 3.0 V
REF
MS
Input Resistance R
REFMS
(Note 6) 5 k
REF
MS
Input Capacitance 15 pF
REF+ Output Voltage V
REF+
V
REF
= +2.5V 3.850 V
COM Output Voltage V
COM
V
REF
= +2.5V 2.600 V
REF- Output Voltage V
REF-
V
REF
= +2.5V 1.350 V
Differential Reference Voltage
V
REF+
-
V
REF
-
V
REF
= +2.5V 2.500 V
DIGITAL INPUTS (D0–D7, RD, WR, CS, CLK, SHDN, CHSHDN, CONVST)
Input-Voltage High V
IH
0.7 x V
DVDD
V
Input-Voltage Low V
IL
0.3 x V
DVDD
V
Input Hysteresis 20 mV
Input Capacitance C
IN
15 pF
Input Current I
IN
V
IN
= 0V or V
DVDD
0.02 ±1 µA
CLOCK-SELECT INPUT (INTCLK/EXTCLK)
Input-Voltage High V
IH
0.7 x V
AVDD
V
Input-Voltage Low V
IL
0.3 x V
AVDD
V
DIGITAL OUTPUTS (D0–D11, EOC, EOLC)
Output-Voltage High V
OH
I
SOURCE
= 0.8mA, Figure 1 V
DVDD
- 0.6 V
Output-Voltage Low V
OL
I
SINK
= 1.6mA, Figure 1 0.4 V
D0–D11 Tri-State Leakage Current RD = high or CS = high 0.06 1 µA
D 0–D 11 Tr i - S tate Outp ut
C ap aci tance
RD = high or CS = high 15 pF
POWER SUPPLIES
Analog Supply Voltage AVDD 4.75 5.25 V
Digital Supply Voltage DVDD 2.70 5.25 V
MAX1304/MAX1305/MAX1306,
all channels selected
55 60
MAX1308/MAX1309/MAX1310,
all channels selected
54 60
Analog Supply Current I
AVDD
MAX1312/MAX1313/MAX1314,
all channels selected
54 60
mA
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +5V, V
DVDD
= +3V, V
AGND
= V
DGND
= 0V, V
REF
= V
REFMS
= +2.5V (external reference), C
REF
= C
REFMS
= 0.1µF, C
REF+
=
C
REF-
= 0.1µF, C
REF+-to-REF-
= 2.2µF || 0.1µF, C
COM
= 2.2µF || 0.1µF, C
MSV
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
lar devices), f
CLK
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C. See Figures 3 and 4.)
MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1304/MAX1305/MAX1306,
all channels selected
1.3 2.6
MAX1308/MAX1309/MAX1310,
all channels selected
1.3 2.6
Digital Supply Current
(C
LOAD
= 100pF) (Note 7)
I
DVDD
MAX1312/MAX1313/MAX1314,
all channels selected
1.3 2.6
mA
I
AVDD
SHDN = DVDD, V
CH
= open 0.6 10
Shutdown Current
(Note 8)
I
DVDD
SHDN = DVDD, RD = WR = high 0.02 1
µA
Power-Supply Rejection Ratio PSRR V
AVDD
= +4.75V to +5.25V 50 dB
TIMING CHARACTERISTICS (Figure 1)
Internal clock, Figure 7 800 900 ns
Time to First Conversion Result t
CONV
External clock, Figure 8 12
CLK
Cycles
Internal clock, Figure 7 200 225 ns
Time to Subsequent Conversions t
NEXT
External clock, Figure 8 3
CLK
Cycles
CONVST Pulse-Width Low
(Acquisition Time)
t
ACQ
(Note 9) Figures 6–10 0.1 1000.0 µs
CS Pulse Width t
CS
Figure 6 30 ns
RD Pulse-Width Low t
RDL
Figures 7, 8, 9 30 ns
RD Pulse-Width High t
RDH
Figures 7, 8, 9 30 ns
WR Pulse-Width Low t
WRL
Figure 6 30 ns
CS to WR t
CTW
Figure 6 (Note 10) ns
WR to CS t
WTC
Figure 6 (Note 10) ns
CS to RD t
CTR
Figures 7, 8, 9 (Note 10) ns
RD to CS t
RTC
Figures 7, 8, 9 (Note 10) ns
Data Access Time
(RD Low to Valid Data)
t
ACC
Figures 7, 8, 9 30 ns
Bus Relinquish Time (RD High) t
REQ
Figures 7, 8, 9 5 30 ns
CLK Rise to EOC Delay t
EOCD
Figure 8 20 ns
CLK Rise to EOLC Fall Delay t
EOLCD
Figure 8 20 ns
CONVST Fall to EOLC Rise Delay t
CVEOLCD
Figures 7, 8, 9 20 ns
Internal clock, Figure 7 50 ns
EOC Pulse Width t
EOC
External clock, Figure 8 1
CLK
Cycle
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +5V, V
DVDD
= +3V, V
AGND
= V
DGND
= 0V, V
REF
= V
REFMS
= +2.5V (external reference), C
REF
= C
REFMS
= 0.1µF, C
REF+
=
C
REF-
= 0.1µF, C
REF+-to-REF-
= 2.2µF || 0.1µF, C
COM
= 2.2µF || 0.1µF, C
MSV
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
lar devices), f
CLK
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C. See Figures 3 and 4.)
MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
6 _______________________________________________________________________________________
Note 1: For the MAX1304/MAX1305/MAX1306, V
IN
= 0 to +5V. For the MAX1308/MAX1309/MAX1310, V
IN
= -5V to +5V. For the
MAX1312/MAX1313/MAX1314, V
IN
= -10V to +10V.
Note 2: All channel performance is guaranteed by correlation to a single channel test.
Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:
for V
CH_
within the input voltage range.
Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (f
CLK
). The external clock through-
put rate is specified with f
CLK
= 16.67MHz and the internal clock throughput rate is specified with f
CLK
= 15MHz. See the
Data Throughput
section for more information.
Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
for V
REF
within the input voltage range.
Note 6: The REF
MS
input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF
MS
input current using:
for V
REFMS
within the input voltage range.
Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave.
Note 8: Shutdown current is measured with the analog input unconnected. The large amplitude of the maximum shutdown current
specification is due to automated test equipment limitations.
Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply.
Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST
and the falling edge of EOLC to a maximum of 1ms.
I
VV
R
REFMS
REFMS
REFMS
=
25.
I
VV
R
REF
REF
REF
=
25.
I
VV
R
CH
CH BIAS
CH
_
_
_
=
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input-Data Setup Time t
DTW
Figure 6 10 ns
Input-Data Hold Time t
WTD
Figure 6 10 ns
External CLK Period t
CLK
Figures 8, 9 0.05 10.00 µs
External CLK High Period t
CLKH
Logic sensitive to rising edges,
Figures 8, 9
20 ns
External CLK Low Period t
CLKL
Logic sensitive to rising edges,
Figures 8, 9
20 ns
External Clock Frequency f
CLK
(Note 11) 0.1 20 MHz
Internal Clock Frequency f
INT
15 MHz
CONVST High to CLK Edge t
CNTC
Figures 8, 9 20 ns
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +5V, V
DVDD
= +3V, V
AGND
= V
DGND
= 0V, V
REF
= V
REFMS
= +2.5V (external reference), C
REF
= C
REFMS
= 0.1µF, C
REF+
=
C
REF-
= 0.1µF, C
REF+-to-REF-
= 2.2µF || 0.1µF, C
COM
= 2.2µF || 0.1µF, C
MSV
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
lar devices), f
CLK
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C. See Figures 3 and 4.)

MAX1304ECM+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 8Ch 1.075Msps 3V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union