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AT91FR40162-CI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
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AT91FR40162
having to desolder the device from the target board. In tri-state mode, all the output pin drivers
of the AT91R40008 microcontroller are disabled.
In tri-state mode, direct access to the Flash via external pins is provided. This enables produc-
tion Flash programming using classical Flash programmers prior to board mounting.
To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles before
the rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by
a resistor of up to 400 kΩ.
NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.
7.5.2 JTAG/ICE Debug
ARM-standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins
TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host
computer via the external ICE interface. In ICE Debug Mode, the ARM7TDMI core responds
with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1
compliant.
7.6 Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the
internal 32-bit address bus and defines three address spaces:
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices (memory or peripherals) controlled by the
EBI
• Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in little-endian mode only.
7.6.1 Internal Memories
The AT91FR40162 microcontroller integrates 256K bytes of internal SRAM. It is 32 bits wide
and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit) accesses
are supported and are executed within one cycle. Fetching either Thumb or ARM instructions
is supported, and internal memory can store two times as many Thumb instructions as ARM
instructions.
The SRAM is mapped at address 0x0 (after the Remap command), allowing ARM7TDMI
exception vectors between 0x0 and 0x20 to be modified by the software.
Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcon-
troller performance and minimizes system power consumption. The 32-bit bus increases the
effectiveness of the use of the ARM instruction set and the processing of data that is wider
than 16 bits, thus making optimal use of the ARM7TDMI advanced performance.
Being able to dynamically update application software in the 256-Kbyte SRAM adds an extra
dimension to the AT91FR40162.
The AT91FR40162 also integrates a 2-Mbyte Flash memory that is accessed via the External
Bus Interface. All data, address and control lines, except for the Chip Select signal, are con-
nected within the device.
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AT91FR40162
7.6.2 Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-
cutes the instruction stored at this address. This means that this address must be mapped in
nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock
cycles before the rising edge of the NRST selects the type of boot memory (see Table 1).
If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled
down externally and NCS0 must be connected to NCSF externally.
The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any
standard PIO line.
7.6.3 Remap Command
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors
to be redefined dynamically by the software, the AT91FR40162 uses a remap command that
enables switching between the boot memory and the internal primary SRAM bank addresses.
The remap command is accessible through the EBI User Interface by writing one in RCB of
EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to
the other external devices (connected to chip selects 1 to 7) is required. The remap operation
can only be changed back by an internal reset or an NRST assertion.
7.6.4 Abort Control
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted when accessing an undefined address in the EBI address space.
No abort is generated when reading the internal memory or by accessing the internal peripher-
als, whether the address is defined or not.
7.6.5 External Bus Interface
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and can be
configured from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte, half-word
and word aligned accesses.
For each of these banks, the user can program:
• Number of wait states
• Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device is too long in releasing the bus)
• Data bus width (8-bit or 16-bit)
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device
(Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-bit memory
(Byte Write Access Mode).
Table 1. Boot Mode Select
BMS Boot Memory
1 External 8-bit memory on NCS0
0 External 16-bit memory on NCS0
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AT91FR40162
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in the case
of single-clock cycle access.
In the AT91FR40162, the External Bus Interface connects internally to the Flash memory.
7.6.6 Flash Memory
The 2-Mbyte Flash memory is organized as 1, 048, 576 words of 16 bits each. The Flash
memory is addressed as 16-bit words via the EBI. It uses address lines A1 - A20.
The address, data and control signals, except the Flash memory enable, are internally inter-
connected. The user should connect the Flash memory enable (NCSF) to one of the active-
low chip selects on the EBI; NCS0 must be used if the Flash memory is to be the boot mem-
ory. In addition, if the Flash memory is to be used as boot memory, the BMS input must be
pulled down externally in order for the processor to perform correct 16-bit fetches after reset.
During boot, the EBI must be configured with correct number of standard wait states. As an
example, five standard wait states are required when the microcontroller is running at 66 MHz.
The user must ensure that all VDDIO, VDDCORE and all GND pins are connected to their
respective supplies by the shortest route. The Flash memory powers-on in read mode. Com-
mand sequences are used to place the device in other operating modes, such as program and
erase.
A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility,
enabling the reset operation to adapt to the application. When this input is at a logic high level,
the memory is in its standard operating mode; a low level on this input halts the current mem-
ory operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end of a program cycle. While a program
cycle is in progress, an attempted read of the last word written will return the complement of
the written data on I/O7. An open-drain NBUSY output pin provides another method of detect-
ing the end of a program or erase cycle. This pin is pulled low while program and erase cycles
are in progress and is released at the completion of the cycle. A toggle bit feature provides a
third means of detecting the end of a program or erase cycle.
The Flash memory is segmented into two memory planes. Reads from one memory plane
may be performed even while program or erase functions are being executed in the other
memory plane. This feature enhances performance by not requiring the system to wait for a
program or erase cycle to complete before a read may be performed.
The Flash memory is divided into 39 sectors for erase operations. To further enhance device
flexibility, an Erase Suspend feature is offered. This feature puts the erase cycle on hold for an
indefinite period and allows the user to read data from, or to write data to, any other sector
within the same memory plane. There is no need to suspend an erase cycle if the data to be
read is in the other memory plane.
The device has the capability to protect data stored in any sector. Once the data protection for
a sector is enabled, the data in that sector cannot be changed while input levels lie between
ground and VDDIO.
An optional VPP pin is available to enhance program/erase times.
A 6-byte command sequence (Enter Single Pulse Program Mode) allows the device to be writ-
ten to directly, using single pulses on the write control lines. This mode (Single-pulse
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

AT91FR40162-CI

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IC MCU 16/32BIT 2MB FLASH 121BGA AT91
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