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2632D–ATARM–15-Sep-05
AT91FR40162
memory resource only. External accesses are performed only to program the encapsulated
Flash.
When starting, PIO input change interrupts are initialized on the RXD lines of both USARTs.
When an interrupt occurs, a Timer Counter channel is started. When the next input change is
detected on the RXD line, the Timer Counter channel is stopped. This is how the first charac-
ter length is measured and the USART can be initiated by taking into account the ratio
between the device master clock speed and the actual communication baud rate speed.
The Programming System, then, can send commands and data following a proprietary proto-
col for the Flash device to be programmed. It is up to the Programming System to erase and
program the first sector of the Flash as the last step of the operation, in order to reduce, to a
minimum, the risk that the Flash Uploader is erased and the power supply shuts down.
Note that in the event that the Flash Uploader is erased from the first sector while the new final
application is not yet programmed, and while the target system power supply is switched off, it
leads to a non-recoverable error and the AT91FR40162 cannot be re-programmed by using
the Flash Uploader.
7.7.2 Programming System
Atmel provides a free Host Loader that runs on an IBM
®
compatible PC under Windows
®
95 or
Windows
®
98 operating system. It can be downloaded from the Atmel Web site and requires
only a serial cable to connect the Host to the Target.
Communications can be selected on either COM1 or COM2 and the serial link speed is limited
to 115200 bauds. Because the serial link is the bottleneck in this configuration, the Flash pro-
gramming lasts 110 seconds per Mbyte.
Reduced programming time can be achieved by using a faster programming system. An AT91
Evaluation Board is capable of running a serial link at up to 500 Kbits/sec and can match the
fastest programming allowed by the Flash, for example, about 40 seconds per Mbyte when the
word programming becomes the bottleneck.
7.8 Peripherals
The AT91FR40162 peripherals are connected to the 32-bit wide Advanced Peripheral Bus.
Peripheral registers are only word accessible. Byte and half-word accesses are not supported.
If a byte or a half-word access is attempted, the memory controller automatically masks the
lowest address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address
space).
7.8.1 Peripheral Registers
The following registers are common to all peripherals:
• Control Register – write only register that triggers a command when a one is written to the
corresponding position at the appropriate address. Writing a zero has no effect.
• Mode Register – read/write register that defines the configuration of the peripheral. Usually
has a value of 0x0 after a reset.
• Data Registers – read and/or write register that enables the exchange of data between the
processor and the peripheral.
• Status Register – read only register that returns the status of the peripheral.
