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2632D–ATARM–15-Sep-05
AT91FR40162
7.9.3 PIO: Parallel I/O Controller
The AT91FR40162 has 32 programmable I/O lines. Six pins are dedicated as general-purpose
I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the
use of available package pins. The PIO controller enables generation of an interrupt on input
change and insertion of a simple input glitch filter on any of the PIO pins.
7.9.4 WD: Watchdog
The Watchdog is built around a 16-bit counter and is used to prevent system lock-up if the
software becomes trapped in a deadlock. It can generate an internal reset or interrupt, or
assert an active level on the dedicated pin NWDOVF. All programming registers are pass-
word-protected to prevent unintentional programming.
7.9.5 SF: Special Function
The AT91FR40162 provides registers that implement the following special functions.
• Chip Identification
• RESET Status
• Protect Mode
7.10 User Peripherals
7.10.1 USART: Universal Synchronous/
Asynchronous Receiver Transmitter
The AT91FR40162 provides two identical, full-duplex, universal synchronous/asynchronous
receiver/transmitters.
Each USART has its own baud rate generator, and two dedicated Peripheral Data Controller
channels. The data format includes a start bit, up to 8 data bits, an optional programmable par-
ity bit and up to 2 stop bits.
The USART also features a Receiver Timeout register, facilitating variable length frame sup-
port when it is working with the PDC, and a Time-guard register, used when interfacing with
slow remote equipment.
7.10.2 TC: Timer Counter
The AT91FR40162 features a Timer Counter block that includes three identical 16-bit timer
counter channels. Each channel can be independently programmed to perform a wide range
of functions including frequency measurement, event counting, interval measurement, pulse
generation, delay timing and pulse width modulation.
The Timer Counter can be used in Capture or Waveform mode, and all three counter channels
can be started simultaneously and chained together.
