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SL28541BZC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
SL28541
......................DOC #: SP-AP-0063 (Rev. AA) Page 10 of 31
4 1 PCI4 Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
3 1 PCI3 Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
2 1 PCI2 Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
1 1 PCI1 Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
0 1 PCI0 Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
Byte 2: Control Register 2 (continued)
Bit @Pup Name Description
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 SRC[T/C]11 Output enable for SRC11
0 = Output Disabled, 1 = Output Enabled
6 1 SRC[T/C]10 Output enable for SRC10
0 = Output Disabled, 1 = Output Enabled
5 1 SRC[T/C]9 Output enable for SRC9
0 = Output Disabled, 1 = Output Enabled
4 1 SRC[T/C]8/CPU2_ITP Output enable for SRC8 or CPU2_ITP
0 = Output Disabled, 1 = Output Enabled
3 1 SRC[T/C]7 Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
2 1 SRC[T/C]6 Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
1 1 Reserved Reserved
0 1 SRC[T/C]4 Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit @Pup Name Description
7 1 SRC[T/C]3 Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
6 1 SRC[T/C]2/SATA Output enable for SRC2/SATA
0 = Output Disabled, 1 = Output Enabled
5 1 SRC[T/C]1/LCD_100M[T/C] Output enable for SRC1/LCD_100M
0 = Output Disabled, 1 = Output Enabled
4 1 SRC[T/C]0/DOT96[T/C] Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
3 1 CPU[T/C]1 Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
2 1 CPU[T/C]0 Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
1 1 PLL1_SS_EN Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0 1 PLL3_SS_EN Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
SL28541
...................... DOC #: SP-AP-0063 (Rev. AA) Page 11 of 31
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 CR#_A_EN Enable CR#_A (clk req)
0 = Disabled, 1 = Enabled,
6 0 CR#_A_SEL Set CR#_A SRC0 or SRC2
0 = CR#_ASRC0, 1 = CR#_ASRC2
5 0 CR#_B_EN Enable CR#_B(clk req)
0 = Disabled, 1 = Enabled,
4 0 CR#_B_SEL Set CR#_B SRC1 or SRC4
0 = CR#_BSRC1, 1 = CR#_BSRC4
3 0 CR#_C_EN Enable CR#_C (clk req)
0 = Disabled, 1 = Enabled
2 0 CR#_C_SEL Set CR#_C SRC0 or SRC2
0 = CR#_CSRC0, 1 = CR#_CSRC2
1 0 CR#_D_EN Enable CR#_D (clk req)
0 = Disabled, 1 = Enabled
0 0 CR#_D_SEL Set CR#_D SRC1 or SRC4
0 = CR#_DSRC1, 1 = CR#_DSRC4
Byte 6: Control Register 6
Bit @Pup Name Description
7 0 CR#_E_EN Enable CR#_E (clk req) SRC6
0 = Disabled, 1 = Enabled
6 0 CR#_F_EN Enable CR#_F (clk req) SRC8
0 = Disabled, 1 = Enabled
5 0 CR#_G_EN Enable CR#_G (clk req) SRC9
0 = Disabled, 1 = Enabled
4 0 CR#_H_EN Enable CR#_H (clk req) SRC10
0 = Disabled, 1 = Enabled
3 0 Reserved Reserved
2 0 Reserved Reserved
1 0 LCD_100_STP_CTRL If set, LCD_100 stop with PCI_STP#
0 = Free running, 1 = PCI_STP# stoppable
0 0 SRC_STP_CTRL If set, SRCs stop with PCI_STP#
0 = Free running, 1 = PCI_STP# stoppable
Byte 7: Vendor ID
Bit @Pup Name Description
7 0 Rev Code Bit 3 Revision Code Bit 3
6 0 Rev Code Bit 2 Revision Code Bit 2
5 0 Rev Code Bit 1 Revision Code Bit 1
4 1 Rev Code Bit 0 Revision Code Bit 0
3 1 Vendor ID bit 3 Vendor ID Bit 3
2 0 Vendor ID bit 2 Vendor ID Bit 2
1 0 Vendor ID bit 1 Vendor ID Bit 1
0 0 Vendor ID bit 0 Vendor ID Bit 0
SL28541
......................DOC #: SP-AP-0063 (Rev. AA) Page 12 of 31
Byte 8: Control Register 8
Bit @Pup Name Description
7 1 Device_ID3 0000 = CK505 Yellow Cover Device, 56-pin TSSOP
0001 = CK505 Yellow Cover Device, 64-pin TSSOP
0010 = CK505 Yellow Cover Device, 48-pin QFN (Reserved)
0011 = CK505 Yellow Cover Device, 56-pin QFN (Reserved)
0100 = CK505 Yellow Cover Device, 64-pin QFN
0101 = CK505 Yellow Cover Device, 72-pin QFN (Reserved)
0110 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
0111 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
1000 = Reserved
1001 = CY28548
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
6 0 Device_ID2
5 0 Device_ID1
4 0 Device_ID0
3 0 Reserved Reserved
2 0 Reserved Reserved
1 1 27M_NSS_OE Output enable for 27M_NSS
0 = Output Disabled, 1 = Output Enabled
0 1 27M_SS_OE Output enable for 27M_SS
0 = Output Disabled, 1 = Output Enabled
Byte 9: Control Register 9
Bit @Pup Name Description
7 0 PCIF_0_with PCI_STP# Allows control of PCIF_0 with assertion of PCI_STP#
0 = Free running PCIF, 1 = Stopped with PCI_STP#
6 HW TME_STRAP Trusted mode enable strap status
0 = Normal, 1 = No overclocking
5 1 REF_DSC1 REF drive strength 1 of 2 (See Byte 17 and 18 for more setting)
0 = Low, 1 = High
4 0 TEST_MODE_SEL Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
3 0 TEST_MODE_ENTRY Allow entry into test mode
0 = Normal operation, 1 = Enter test mode
2 1 I2C_VOUT<2> Differential Amplitude Configuration
I2C_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
010 = 0.77V
011 = 082V
100 = 0.86V
101 = 0.90V (default)
110 = 0.93V
111 = unused
1 0 I2C_VOUT<1>
0 1 I2C_VOUT<0>
Byte 10: Control Register 10
Bit @Pup Name Description
7 HW GCLK_SEL latch Readback of GCLK_SEL latch
0 = DOT96/LCD_100, 1 = SRC0/27 MHz
6 1 PLL3_EN PLL3 power down
0 = Power down, 1 = Power up
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

SL28541BZC

Mfr. #:
Buy SL28541BZC
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Montevina
Lifecycle:
New from this manufacturer.
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