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SL28541BZC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
SL28541
......................DOC #: SP-AP-0063 (Rev. AA) Page 13 of 31
5 1 PLL2_EN PLL2 power down
0 = Power down, 1 = Power up
4 1 SRC_DIV_EN SRC divider disable
0 = Disabled, 1 = Enabled
3 1 PCI_DIV_EN PCI divider disable
0 = Disabled, 1 = Enabled
2 1 CPU_DIV_EN CPU divider disable
0 = Disabled, 1 = Enabled
1 1 CPU1 Stop Enable Enable CPU_STP# control of CPU1
0 = Free running, 1= Stoppable
0 1 CPU0 Stop Enable Enable CPU_STP# control of CPU0
0 = Free running, 1= Stoppable
Byte 10: Control Register 10 (continued)
Bit @Pup Name Description
Byte 11: Control Register 11
Bit @Pup Name Description
7 0 Reserved Reserved
6 0 Reserved Reserved
5 0 Reserved Reserved
4 0 Reserved Reserved
3 0 Reserved Reserved
2 0 Reserved Reserved
1 0 Reserved Reserved
0 0 Reserved Reserved
Byte 12: Byte Count
Bit @Pup Name Description
7 0 Reserved Reserved
6 0 Reserved Reserved
5 0 BC5 Byte count register for block read operation.
The default value for Byte count is 19.
In order to read beyond Byte 19, the user should change the byte count
limit.to or beyond the byte that is desired to be read.
41 BC4
30 BC3
20 BC2
11 BC1
01 BC0
Byte 13: Control Register 13
Bit @Pup Name Description
7 1 USB_BIT1 USB drive strength 1 of 3(See Byte 17 for more setting)
0 = Low, 1= High
6 1 PCI/ PCIF_BIT1 PCI drive strength 1 of 3(See Byte 17 & 18 for more setting)
0 = Low, 1 = High
5 0 PLL1_Spread Select percentage of spread for PLL1
0 = 0.5%, 1=1%
4 1 SATA_SS_EN Enable SATA spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
3 1 CPU[T/C]2 Allow control of CPU2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
SL28541
......................DOC #: SP-AP-0063 (Rev. AA) Page 14 of 31
2 1 SE1/SE2_BIT_1 SE1 and SE2 Drive Strength Setting 1 of 3 (See Byte 17 and 18 for more setting)
0 = Low, 1= High
1 1 Reserved Reserved
0 1 SW_PCI SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are
resumed in a synchronous manner with no short pulses.
Byte 13: Control Register 13 (continued)
Bit @Pup Name Description
Byte 14: Control Register 14
Bit @Pup Name Description
7 0 CPU_DAF_N7 If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
6 0 CPU_DAF_N6
5 0 CPU_DAF_N5
4 0 CPU_DAF_N4
3 0 CPU_DAF_N3
2 0 CPU_DAF_N2
1 0 CPU_DAF_N1
0 0 CPU_DAF_N0
Byte 15: Control Register 15
Bit @Pup Name Description
7 0 CPU_DAF_N8 See Byte 14 for description
6 0 CPU_DAF_M6 If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
5 0 CPU_DAF_M5
4 0 CPU_DAF_M4
3 0 CPU_DAF_M3
2 0 CPU_DAF_M2
1 0 CPU_DAF_M1
0 0 CPU_DAF_M0
Byte 16: Control Register 16
Bit @Pup Name Description
7 0 PCI-E_N7 PCI-E Dial-A-Frequency
®
Bit N7
6 0 PCI-E_N6 PCI-E Dial-A-Frequency Bit N6
5 0 PCI-E_N5 PCI-E Dial-A-Frequency Bit N5
4 0 PCI-E_N4 PCI-E Dial-A-Frequency Bit N4
3 0 PCI-E_N3 PCI-E Dial-A-Frequency Bit N3
2 0 PCI-E_N2 PCI-E Dial-A-Frequency Bit N2
1 0 PCI-E_N1 PCI-E Dial-A-Frequency Bit N1
0 0 PCI-E_N0 PCI-E Dial-A-Frequency Bit N0
SL28541
......................DOC #: SP-AP-0063 (Rev. AA) Page 15 of 31
Byte 18: Control Register 18
Byte 17: Control Register 17
Bit @Pup Name Description
7 0 SMSW_EN Enable Smooth Switching
0 = Disabled, 1= Enabled
6 0 SMSW_SEL Smooth switch select
0 = CPU_PLL, 1 = SRC_PLL
5 0 SE1/SE2_BIT0 SE1 and SE2 drive strength Setting 2 of 3(see Byte 18 for more setting)
0 = Low, 1= High
4 0 Prog_PCI-E_EN Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
3 0 Prog_CPU_EN Programmable CPU frequency enable
0 = Disabled, 1= Enabled
2 0 REF_BIT0 REFdrive strength strength Setting 2 of 3(see Byte 18 for more setting)
0 = Low, 1= High
1 0 USB_BIT0 USB drive strength strength Setting 2 of 3(see Byte 18 for more setting)
0 = Low, 1= High
0 0 PCI/ PCIF_BIT0 PCI drive strength strength Setting 2 of 3(see Byte 18 for more setting)
0 = Low, 1= High
7 0 REF_BIT2 Drive Strength Control
6 0 RESERVED
5 1 RESERVED
4 0 RESERVED
3 0 USB_BIT2
2 0 PCI/PCIF_BIT2
1 0 SE1/SE2_BIT2
0 0 RESERVED
Table 5. Output Driver Status during PCI-STP# and CPU-STP#
PCI_STP# Asserted CPU_STP# Asserted SMBus OE Disabled
Single-ended Clocks Stoppable Driven low Running Driven low
Non stoppable Running Running
Differential Clocks Stoppable Clock driven high Clock driven high Clock driven Low or 20K
pulldown
Clock# driven low Clock# driven low
Non stoppable Running Running
Table 6. Output Driver Status
All Single-ended Clocks
All Differential Clocks except
CPU1 CPU1
w/o Strap w/ Strap Clock Clock# Clock Clock#
Latches Open State Low Hi-z Low or 20K pulldown Low Low or 20K pulldown Low
Powerdown Low Hi-z Low or 20K pulldown Low Low or 20K pulldown Low
M1 Low Hi-z Low or 20K pulldown Low Running Running
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

SL28541BZC

Mfr. #:
Buy SL28541BZC
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Montevina
Lifecycle:
New from this manufacturer.
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