........................DOC #: SP-AP-0063 (Rev. AA) Page 7 of 31
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CKPWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CKPWRGD and indicates that VTT voltage is stable then FSA,
FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CKPWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CKPWRGD transitions are ignored except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
48 NC NC No Connect
49 VDD_CPU_IO PWR IO Power supply for CPU outputs.
50 CPU1# O, DIF Differential CPU clock outputs. (
Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
51 CPU1 O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
52 VSS_CPU GND Ground for outputs.
53 CPU#0 O, DIF Differential CPU clock outputs.
54 CPU0 O, DIF Differential CPU clock outputs.
55 VDD_CPU PWR 3.3V Power supply for CPU PLL.
56 CKPWRGD/PD# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
57 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58 VSS_REF GND Ground for outputs.
59 XOUT O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)
60 XIN/CLKIN I 14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.
61 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
62 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.
Selects test mode if pulled to V
IHFS_C
when CKPWRGD is asserted HIGH. Refer
to DC Electrical Specifications table for V
ILFS_C
, V
IMFS_C
, V
IHFS_C
specifications.
63 SMB_DATA I/O SMBus compatible SDATA.
64 SMB_CLK I SMBus compatible SCLOCK.
64 TSSOP Pin Definition (continued)
Pin No. Name Type Description
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC FSB FSA CPU SRC PCIF/PCI 27MHz REF DOT96 USB
0 0 0 266 MHz
100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz
0 0 1 133 MHz
0 1 0 200 MHz
0 1 1 166 MHz
1 0 0 333 MHz
1 0 1 100 MHz
1 1 0 400 MHz
1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
