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SL28541BZC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
SL28541
........................DOC #: SP-AP-0063 (Rev. AA) Page 4 of 31
27 VDD_PLL3_IO PWR IO Power supply for PLL3 outputs.
28 SRC2/SATA O, DIF 100MHz Differential serial reference clocks.
29 SRC2#/SATA# O, DIF 100MHz Differential serial reference clocks.
30 VSS_SRC GND Ground for outputs.
31 SRC3/OE#_0/2_B I/O,
Dif
100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via
I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock)
32 SRC3#OE#_1/4_B I/O,
Dif
100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via
I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock)
33 VDD_SRC_IO PWR IO power supply for SRC outputs.
34 SRC4 O, DIF 100MHz Differential serial reference clocks.
35 SRC4# O, DIF 100MHz Differential serial reference clocks.
36 VSS_SRC GND Ground for outputs.
37 SRC9 O, DIF 100MHz Differential serial reference clocks.
38 SRC9# O, DIF 100MHz Differential serial reference clocks.
39 SRC11#/OE#_9 I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
(Default SRC11, 100MHz clock)
40 SRC11/OE#_10 I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.
(Default SRC11, 100MHz clock)
41 SRC10 O, DIF 100MHz Differential serial reference clocks.
42 SRC10# O, DIF 100MHz Differential serial reference clocks.
43 VDD_SRC_IO PWR IO Power supply for SRC outputs.
44 CPU_STP# I 3.3V tolerant input for stopping CPU outputs
45 PCI_STP# I 3.3V tolerant input for stopping PCI and SRC outputs
46 VDD_SRC PWR 3.3V Power supply for SRC PLL.
47 SRC6# O, DIF 100MHz Differential serial reference clocks.
48 SRC6 O, DIF 100MHz Differential serial reference clocks.
49 VSS_SRC GND Ground for outputs.
50 SRC7#/OE#_6 I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
(Default SRC7, 100MHz clock).
51 SRC7/OE#_8 I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
(Default SRC7, 100MHz clock).
52 VDD_SRC_IO PWR 0.7V power supply for SRC outputs.
53 SRC8#/CPU2#_ITP# O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
54 SRC8/CPU2_ITP O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
55 NC NC No Connect
56 VDD_CPU_IO PWR IO Power supply for CPU outputs.
57 CPU1# O, DIF Differential CPU clock outputs. (
Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
58 CPU1 O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
59 VSS_CPU GND Ground for outputs.
64 QFN Pin Definitions (continued)
Pin No. Name Type Description
SL28541
........................DOC #: SP-AP-0063 (Rev. AA) Page 5 of 31
60 CPU#0 O, DIF Differential CPU clock outputs.
61 CPU0 O, DIF Differential CPU clock outputs.
62 VDD_CPU PWR 3.3V Power supply for CPU PLL.
63 CKPWRGD/PD# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
64 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
64 QFN Pin Definitions (continued)
Pin No. Name Type Description
64 TSSOP Pin Definition
Pin No. Name Type Description
1 PCI0/OE#_0/2_A I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or
SRC2. (Default PCI0, 33MHz clock)
2 VDD_PCI PWR 3.3V Power supply for PCI PLL.
3 PCI1/OE#_1/4_A I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or
SRC4. (Default PCI1, 33MHz clock)
4 PCI2/TME I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
5 PCI3 O, SE, 33 MHz clock.
6 PCI4 / GCLK_SEL I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source on pin
13, 14, 17and 18
Sampled on CKPWRGD assertion
7 PCIF_0/ITP_EN I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled
on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8 VSS_PCI GND Ground for outputs.
9 VDD_48 PWR 3.3V Power supply for outputs and PLL.
10 USB_48/FSA I/O 3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output.
(Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications)
11 VSS_48 GND Ground for outputs.
12 VDD_IO PWR 0.7V Power supply for outputs.
13 SRC0/DOT96 O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
14 SRC0#/DOT96# O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output.
(Selected via I2C default is SRC0)
15 VSS_IO GND Ground for PLL2.
16 VDD_PLL3 PWR 3.3V Power supply for PLL3
GCLK_SEL Pin13 Pin14 Pin17 Pin 18
0 DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
1 SRCT0 SRCC0 27M_NSS 27M_SS
SL28541
........................DOC #: SP-AP-0063 (Rev. AA) Page 6 of 31
17 SRC1/LCD100/27_NSS O, DIF,
SE
True 100 MHz differential serial reference clock output/True 100 MHz LCD video
clock output / Non-spread 27-MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
18 SRC1#/LCD100#/27_SS O, DIF,
SE
Complementary 100 MHz differential serial reference clock output/Complementary
100 MHz LCD video clock output /Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
19 VSS_PLL3 GND Ground for PLL3.
20 VDD_PLL3_IO PWR IO Power supply for PLL3 outputs.
21 SRC2/SATA O, DIF 100MHz Differential serial reference clocks.
22 SRC2#/SATA# O, DIF 100MHz Differential serial reference clocks.
23 VSS_SRC GND Ground for outputs.
24 SRC3/OE#_0/2_B I/O,
Dif
100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via
I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock)
25 SRC3#OE#_1/4_B I/O,
Dif
100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via
I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock)
26 VDD_SRC_IO PWR IO power supply for SRC outputs.
27 SRC4 O, DIF 100MHz Differential serial reference clocks.
28 SRC4# O, DIF 100MHz Differential serial reference clocks.
29 VSS_SRC GND Ground for outputs.
30 SRC9 O, DIF 100MHz Differential serial reference clocks.
31 SRC9# O, DIF 100MHz Differential serial reference clocks.
32 SRC11#/OE#_9 I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
(Default SRC11, 100MHz clock)
33 SRC11/OE#_10 I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10.
(Default SRC11, 100MHz clock)
34 SRC10 O, DIF 100MHz Differential serial reference clocks.
35 SRC10# O, DIF 100MHz Differential serial reference clocks.
36 VDD_SRC_IO PWR IO Power supply for SRC outputs.
37 CPU_STP# I 3.3V tolerant input for stopping CPU outputs
38 PCI_STP# I 3.3V tolerant input for stopping PCI and SRC outputs
39 VDD_SRC PWR 3.3V Power supply for SRC PLL.
40 SRC6# O, DIF 100MHz Differential serial reference clocks.
41 SRC6 O, DIF 100MHz Differential serial reference clocks.
42 VSS_SRC GND Ground for outputs.
43 SRC7#/OE#_6 I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
(Default SRC7, 100MHz clock).
44 SRC7/OE#_8 I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
(Default SRC7, 100MHz clock).
45 VDD_SRC_IO PWR 0.7V power supply for SRC outputs.
46 SRC8#/CPU2#_ITP# O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
47 SRC8/CPU2_ITP O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
64 TSSOP Pin Definition (continued)
Pin No. Name Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

SL28541BZC

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Buy SL28541BZC
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Montevina
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