MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
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microcontroller acts as the master in an SPI application.
CS is asserted low by the microcontroller to initiate a
transfer and deasserted high to terminate a transfer.
DIN transfers input data to the MAX6916 from the
microcontroller, and DOUT transfers output data from
the MAX6916 to the microcontroller. SCLK is used to
synchronize data movement between the microcon-
troller and the MAX6916. SCLK, which is generated by
the microcontroller, is active only during address and
data transfer to any device on the SPI bus. The inactive
clock polarity is usually programmable on the micro-
controller side of the SPI interface. For the MAX6916,
input data (DIN) is latched on the positive edge and
output data (DOUT) is shifted out on the negative edge.
There is one clock for each bit transferred. Address
and data bits are transferred in groups of eight. Figure
2 shows an SPI bus timing diagram.
The SPI protocol allows for one of four combinations of
serial clock phase and polarity from the microcontroller,
through a 2-bit selection in its SPI control register. The
clock polarity is specified by the CPOL control bit,
which selects active-high or active-low clock, and has
no significant effect on the transfer format. The clock-
phase control bit, CPHA, selects one of two different
transfer formats. The clock phase and polarity must be
identical for the master and the slave. For the
MAX6916, set the control bits to CPHA = 1 and CPOL =
1. This setting configures the system for data to be
launched on the negative edge of SCLK and sampled
on the positive edge. With CPHA equal to 1, CS can
remain low between successive data byte transfers,
allowing burst-mode data transfers to occur.
Address and data bytes are shifted, most significant bit
(MSB) first, into the serial data input DIN of the
MAX6916 and out of the serial data output DOUT. Data
is shifted out at the negative edge of SCLK and shifted
in or sampled at the positive edge of SCLK. Any trans-
fer requires the address of the byte to be followed by 1
or more bytes of data. Data is transferred out of DOUT
for a read operation and into DIN for a write operation.
When not transferring data out, DOUT is put into a high-
impedance state (Figure 2).
To maximize battery life and prevent erroneous data
from being entered into the MAX6916, the serial bus
interface is disabled when V
CC
is below V
RST
or when
RESET is active.
In order to initiate SPI communications with the
MAX6916, CS needs to be driven low, after which an
address/command byte must be input. The
address/command byte specifies the register to or from
which information is to be transferred, as well as the
nature of the transfer (read or write). After the
address/command byte, 1 or more data bytes can be
written or read. For a single-byte transfer, 1 byte is writ-
ten or read and then CS is driven high by the microcon-
troller (Figures 3 and 5). For a multiple-byte transfer,
however, multiple bytes can be read or written to the
MAX6916 after the address/command byte has been
written (Figures 4 and 6). In the case of burst operation,
each read or write cycle causes the RTC register or
RAM address to automatically increment. Incrementing
continues (maximum value is 96 for RAM and 8 for reg-
ister bank) until SPI transmission is terminated. To ter-
minate the SPI transmission, drive CS high.
