MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1V
OUT
Supply Output for External SRAM or Other ICs Requiring Use of Backup Battery Power. When V
CC
rises
above the reset threshold or above V
BATT
, V
OUT
is connected to V
CC
. When V
CC
falls below V
RESET
and
V
BATT
, V
BATT
is connected to V
OUT
. Connect a 0.1µF low-leakage bypass capacitor from V
OUT
to GND.
Leave open if not used.
2 TEST
External Battery Test. Active high for 1s during each battery test. Intended to drive an external MOSFET
or bipolar transistor for an external battery-test configuration. External test must be selected in the control
register to use TEST; otherwise, it remains low. Leave open if not used.
3 TRIP
External Trip Set. If a different battery-low threshold is desired other than the internal POR default of
V
BTP
, then connect R
SET+
between V
BATT
and TRIP and R
SET-
between TRIP and the drain or collector of
an external transistor whose base or gate is connected to TEST; see Figure 14 (see the Battery Test
section). External test must be selected in the control register to use TRIP. Leave open if not used.
4
BATT_ON
Open-Drain, Battery-On Indicator. BATT_ON is active low when the MAX6916 is powered from V
BATT
.
5 CE_IN Chip-Enable Input. The input to the chip-enable gating circuitry. Connect CE_IN to GND if unused.
6 MR
Manual-Reset Input. A logic-low on MR asserts RESET. RESET remains asserted as long as MR is low
and for t
RP
after MR returns high. The active-low MR input has an internal pullup resistor. MR can be
driven from a TTL- or CMOS-logic line or shorted to ground with a switch. Internal debouncing circuitry
ensures noise immunity. Leave MR open if unused.
7 WDI
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the
internal watchdog timer runs out and RESET is asserted. The internal watchdog timer clears while RESET
is asserted or when WDI sees a rising or falling edge. The watchdog function can be disabled from the
control register. The timeout period is configurable in the control register for 200ms or 1.6s.
8 GND Ground
9 X1 32.768kHZ Crystal-Oscillator Input
10 X2 32.768kHZ Crystal-Oscillator Output
