MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
26 ______________________________________________________________________________________
Battery-Test Control Register
and Other Test Options
There are two warning formats for the BATT_LO and
BATT_ON outputs. By setting D0 (BATT ON BLINK)
and/or D1 (BATT LO BLINK) in the control register to
one, the respective warning output toggles on every
0.5s and off every 0.5s when set to active low by the
internal MAX6916 logic. This setting allows a more
noticeable warning indicator in systems where an LED
is connected as a status or warning light for the end
user. The POR default settings of zero leave these out-
puts set to logic-low when they are active.
D5 (INT/EXT TEST) selects whether the battery test cir-
cuit is configured as internal or external (Table 1). If D5
is set to zero (default value), then the internal resistor-
divider is used between V
BATT
and GND to select the
battery-low trip point (Figure 14). The internal resistors,
R
SET+_INT
and R
SET-_INT
, are used to divide V
BATT
in
half, as well as to provide the battery-test-load resis-
tance of 0.91MΩ (typ).
If D5 (INT/EXT TEST) is set to one, then the two external
resistors, R
SET+_EXT
and R
SET-_EXT
, are used to divide
V
BATT
down to the ratio for a trip point set at TRIP of
1.24V (V
TRIP
) (typ). R
SET+_EXT
plus R
SET-_EXT
in series
provide the load resistance used during the 1s every-
24hr-battery test. If additional load resistance is
desired, then an external load resistor, R
LOAD_EXT
, can
be placed between V
BATT
and the collector or drain of
the transistor driven by TEST. The equivalent load resis-
tance used to test the battery is then R
LOAD_EXT
in par-
allel with the series combination of R
SET+_EXT
plus
R
SET-_EXT
. In this mode, the internal resistors are
removed from TRIP and are not used as a load during
the battery-test pulse. TEST pulses high to perform the
battery test and remains low between tests.
One final battery-test feature of the MAX6916 is the
software write address/command of 0Dh that forces a
1s battery test to be performed every time it is sent.
Applications Information
Crystal Selection
Connect a 32.768kHz watch crystal directly to the
MAX6916 through pins 9 and 10 (X1, X2) (Figure 17).
Use a crystal with a specified load capacitance (C
L
) of
6pF. Refer to Applications Note 616: Considerations for
Maxim Real-Time Clock Crystal Selection from the
Maxim website (www.maxim-ic.com) for more informa-
tion regarding crystal parameters and crystal selection,
as well as a list of crystal manufacturers.
When designing the PC board, keep the crystal as close
to the X1 and X2 pins of the MAX6916 as possible. Keep
the trace lengths short and small to reduce capacitive
loading and prevent unwanted noise pickup. Place a
guard ring around the crystal and connect the ring to
ground to help isolate the crystal from unwanted noise
pickup. Keep all signals out from beneath the crystal and
the X1 and X2 pins to prevent noise coupling. Finally, an
additional local ground plane on an adjacent PC board
layer can be added under the crystal to shield it from
unwanted pickup from traces on other layers of the board.
This plane should be isolated from the regular PC board
ground, connected to the GND pin of the MAX6916, and
needs to be no larger than the perimeter of the guard ring.
Ensure that this ground plane does not contribute to sig-
nificant capacitance between the signal line and ground
on the connections that run from X1 and X2 to the crystal.
See Figure 18.
