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MAX6916EO50+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
22 ______________________________________________________________________________________
Chip-Enable Gating
Internal gating of chip-enable (CE) signals prevents
erroneous data from corrupting external SRAM in the
event of an undervoltage condition. The MAX6916 uses
a transmission gate from CE_IN to CE_OUT (Figure 11).
During normal operation (RESET inactive), the transmis-
sion gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes disabled,
preventing erroneous data from corrupting the external
SRAM. The short CE propagation delay from CE_IN to
CE_OUT enables the MAX6916 to be used with most
microprocessors. If CE_IN is low when reset asserts,
CE_OUT remains low for t
RCE
to permit completion of
the current write cycle.
Chip-Enable Input
The CE transmission gate is disabled and CE_IN is
high impedance (disabled mode) while RESET is
active. During a power-down sequence when V
CC
passes the reset threshold, the CE transmission gate
disables and CE_IN immediately becomes high imped-
ance if the voltage at CE_IN is high. If CE_IN is low
when RESET becomes active, the CE transmission gate
disables at the moment CE_IN goes high or t
RCE
after
RESET is active, whichever occurs first (see the Chip-
Enable Timing section). This condition permits the cur-
rent write cycle to complete during power-down. The
CE transmission gate remains disabled and CE_IN
remains high impedance (regardless of CE_IN activity)
for most of the reset-timeout period (t
RST
) any time a
RESET is generated. When the CE transmission gate is
enabled, the impedance of CE_IN appears as a 46Ω
(typ) load in series with the load at CE_OUT.
The propagation delay through the CE transmission
gate depends on V
CC
, the source impedance of the
driver connected to CE_IN, and the loading on
CE_OUT (see the Chip-Enable Propagation Delay vs.
CE_OUT Load Capacitance graph in the Typical
Operating Characteristics). For minimum propagation
delay, the capacitive load at CE_OUT should be mini-
mized, and a low-output-impedance driver should be
used on CE_IN (Figure 12).
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE OF
PROGRAM LOOP
SET WDI LOW
RETURN
Figure 10. Watchdog Flow Diagram
MAX6916
CHIP-ENABLE
OUTPUT
CONTROL
RESET
GENERATOR
V
OUT
CE_OUTCE_IN
Figure 11. Chip-Enable Gating
MAX6916
25Ω EQUIVALENT
SOURCE IMPEDANCE
50Ω CABLE
50Ω
3.6V
V
CC
C
L
10pF
GND
V
CC
50Ω
CE_IN CE_OUT
BATT
C
L
INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE
Figure 12. Propagation Delay Test Circuit
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
______________________________________________________________________________________ 23
Chip-Enable Output
When the CE transmission gate is enabled, the imped-
ance seen at CE_OUT is equivalent to a 46Ω (typ)
resistor in series with the source driving CE_IN. In the
disabled mode, the transmission gate is off and an
active pullup connects CE_OUT to V
OUT
(see Figures
11 and 13). This pullup turns off when the transmission
gate is enabled.
Test Configuration Register
This is a read-only register.
Data Valid Bit
DATA VALID has a POR setting of zero, indicating that
the data in the MAX6916 RTC is not guaranteed to be
valid (Table 1). A read of the status register sets the
DATA VALID bit to one, indicating valid data in the
MAX6916 RTC. In a system that uses a backup power
supply, the DATA VALID bit should be set to one by the
system software on first system power-up by reading the
status register. After that, any time the system recovers
from a reset condition caused by V
CC
< V
RST
, the DATA
VALID bit can be read to see if the data stored during
operation from the backup power supply is still valid (i.e.,
the backup power supply did not drop out). A one indi-
cates valid data, and a zero indicates corrupted data.
Any time the internal supply to the MAX6916 (either
V
BATT
or V
CC
depending upon the operating conditions)
drops below 1.5V to 1.6V (typ), the DATA VALID bit is set
to zero even if it has recently been set by a read of the
status register.
Battery Test
Battery-Test Normal Operation
In normal operation, the battery-test circuitry uses the
control register POR settings of INT/EXT TEST, which is
set to logic-low as default (Table 1). In this mode, all bat-
tery-test load resistors and threshold settings are internal.
When V
CC
rises above V
RST
, the MAX6916 automatically
performs one power-on battery monitor test. Additionally,
a battery check is performed every time that a reset is
issued, either from a manual reset or from a watchdog
timeout. After that, periodic battery voltage monitoring at
the factory-programmed time interval of 24hr begins while
V
CC
is applied.
V
CC
RESET
CE_OUT
CE_IN
2.0V
V
RST
t
RP
t
RP
V
BATT
V
CC
t
CED
t
RCE
t
RPD
V
RST
Figure 13. Chip-Enable Timing Diagram
MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
24 ______________________________________________________________________________________
After each 24hr period (t
BTCN
) has elapsed, the
MAX6916 connects V
BATT
to an internal 0.91MΩ (typ)
test resistor (R
SET+_INT
+ R
SET-_INT
) for 1s (t
BTPW
)
(Figure 14). During this 1s, if V
BATT
falls below the fac-
tory-programmed battery trip point V
BTP
, the open-
drain, battery-low output, BATT_LO, is asserted active
low and the BATT LO bit in the status register is set to
one. The BATT LO output can be register selected to
toggle at a 1Hz rate (0.5s on, 0.5s off) when active.
Once BATT LO is active, the 24hr tests stop until a
fresh battery is inserted and BATT LO is cleared by
writing any data to the battery test register at address
0x0D (Figure 15). Writing to this register performs a
battery test and provided that the fresh battery is not
low, deactivates the BATT LO output and resets BATT
LO in the status register. Normal 24hr testing resumes.
If a different load or BATT LO thresholds are desired for
testing the backup battery, then external program resis-
tors can be used in conjunction with the TRIP and TEST
inputs (see the Battery-Test Control Register and Other
Test Options section).
Battery replacement following BATT_LO activation
should be done with V
CC
nominal and not in battery-
backup mode so that SRAM data is not lost.
Alternatively, if SRAM data need not be saved, the bat-
tery can be replaced with the V
CC
supply removed. If a
battery is replaced in battery-backup mode, sufficient
time must be allowed for the voltage on the V
OUT
out-
put to decay to zero. This timing ensures that the fresh-
ness-seal mode of operation has been reset and is
active when V
CC
is powered up again. If insufficient
time is allowed, then V
CC
must exceed V
BATT
during
the subsequent power-up to ensure that the MAX6916
has left battery-backup mode (Figure 16).
The MAX6916 does not constantly monitor an attached
battery because such monitoring would drastically
reduce the life of the battery. As a result, the MAX6916
only tests the battery for 1s every 24hr. If a good bat-
tery (one that has not been previously flagged with
BATT_LO) is removed between battery tests, the
MAX6916 does not immediately sense the removal and
does not activate BATT_LO until the next-scheduled
battery test. For this reason, a software-commanded
battery test should be performed after a battery
replacement by writing any data to the battery-test reg-
ister at address 0Dh.
MAX6916
1.24V
V
CC
BATT_LO
CONTROL
LOGIC
R
SET+_INT
480kΩ
R
SET-_INT
430kΩ
V
OUT
INT/EXT
TEST = 0
(±5mA)
BATT
TEST
TEST
TRIP
V
BATT
BATT_LO
R
SET+_EXT
R
LOAD_EXT
(OPTIONAL)
R
SET-_EXT
Q
EXT
INT/EXT
TEST
Figure 14. MAX6916 Battery Load and Test Circuit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

MAX6916EO50+T

Mfr. #:
Buy MAX6916EO50+T
Manufacturer:
Maxim Integrated
Description:
Real Time Clock Integrated Circuits (ICs)
Lifecycle:
New from this manufacturer.
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