MAX6916
SPI-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
18 ______________________________________________________________________________________
Clock-Burst Mode
Addressing the clock-burst register specifies burst-
mode operation. In this mode, the first eight clock/cal-
endar registers (seven timekeeping and the control
register) can be consecutively read or written to by
using the address/command byte 00h for a write or 80h
for a read (Table 1). If the write-protect bit is set to one
when a write-clock/calendar-burst mode is specified,
no data transfer occurs to any of the seven timekeeping
registers or the control register. When writing to the
clock/calendar registers in the burst mode, the first
eight registers must be written to for the data to be
transferred; see Table 2.
RAM
The static RAM consists of 96 x 8 bits addressed con-
secutively in the RAM address/command space.
Address/commands (1Fh to 7Eh) are used for RAM
writes and address/commands (9Fh to FEh) are used
for RAM reads (Table 2).
RAM-Burst Mode
Sending the RAM burst address/command (7Fh for
write, FFh for read) specifies burst-mode operation. In
this mode, the 96 RAM locations can be consecutively
read or written to starting with bit 7 of address/com-
mand 1Fh for writes, and 9Fh for reads. A burst read
outputs all 96 bytes of RAM. When writing to RAM in
burst mode, it is not necessary to write all 96 bytes for
the data to transfer; each complete byte written is
transferred to the RAM. When reading from RAM, data
is output until all 96 bytes have been read, or until the
CS is driven high.
Status Register
The status register contains individual bits for monitor-
ing the status of several functions of the MAX6916. Bits
D0–D3 are unused and always read zero (Table 1). D4
(ALM OUT) reflects the state of the alarm function; see
the Alarm Function section for details. D5 (BATT LO)
indicates the state of the battery connected to V
BATT
;
see the Battery Test section for more information. D6
(DATA VALID) alerts the user if all power was lost. See
the Data Valid Bit section for details. D7 (XTAL FAIL) is
the output of the crystal-fail detect circuit. See the
Crystal-Fail Detect section for details.
Power Control
V
BATT
provides power as a battery backup. V
CC
pro-
vides the primary power in dual-supply systems where
V
BATT
is connected as a backup source to maintain
timekeeping in the absence of primary power. When
V
CC
rises above the reset threshold, V
RST
, V
CC
powers
the MAX6916. When V
CC
falls below the reset thresh-
old, V
RST
, and is less than V
TRD
, V
BATT
powers the
MAX6916. If V
CC
falls below the reset threshold, V
RST
,
and is more than V
TRU
, V
CC
still powers the MAX6916.
The V
CC
slew rate in power-down is limited to 10V/ms
(max) for proper data retention.
V
OUT
Function
V
OUT
is an output supply voltage for battery-backed-up
devices such as SRAM. When V
CC
rises above the
reset threshold or is greater than V
BATT
,V
OUT
connects
to V
CC
(Figure 16). When V
CC
falls below V
RST
and
V
BATT
, V
OUT
connects to V
BATT
. There is a typical
±100mV hysteresis associated with the switching
between V
CC
and V
BATT
on the V
OUT
output. Connect
a 0.1µF capacitor from V
OUT
to GND.
Power-On Reset (POR)
The MAX6916 contains an integral POR circuit that
ensures all registers are reset to a known state on power-
up. Once either V
CC
or V
BATT
rises above 1.6V (typ), the
POR circuit releases the registers for normal operation.
When V
CC
or V
BATT
drops to less than 0.9V (typ), the
MAX6916 resets all register contents to the POR defaults.
Oscillator Start Time
The MAX6916 oscillator typically takes 1s to 2s to begin
oscillating. To ensure the oscillator is operating correct-
ly, the system software should validate proper time-
keeping. This validation is accomplished by reading
the seconds register. Any reading with more than 0s,
from the POR value of 0s, is a validation of proper startup.
Alarm-Generation Function
The alarm function is configured using the alarm-con-
figuration register and the alarm-threshold registers
(Tables 1 and 2). Writing a one to D7 (ONE SEC) in the
alarm-configuration register sets the alarm function to
occur once every second, regardless of any other set-
ting in the alarm-configuration register or in any of the
alarm-threshold registers. When the alarm is triggered,
D4 (ALM OUT) in the status register is set to one and
the open-drain alarm output ALM goes low. The alarm
is cleared by reading or writing to the alarm-configura-
tion register or by reading or writing to any of the alarm-
threshold registers. This process resets the ALM output
to a high and the ALM OUT bit to zero.
When D7 (ONE SEC) is set to zero in the alarm-configu-
ration register, then the alarm function is set by the
remaining bits in the alarm-configuration register and
the contents of the respective alarm-threshold register.
For example, writing 01h (0000 0001) to the alarm-con-
figuration register causes the alarm to trigger every
time the seconds-timekeeping register matches the
seconds alarm-threshold register (i.e., once every
minute on a specific second). Writing 02h (0000 0010)
to the alarm-configuration register causes the alarm to
