M48T201Y, M48T201V Operation
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Table 4. Write mode AC characteristics
2.4 Data retention mode
With valid V
CC
applied, the M48T201Y/V can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the M48T201Y/V will automatically
deselect, write protecting itself (and any external SRAM) when V
CC
falls between V
PFD
(max) and V
PFD
(min). This is accomplished by internally inhibiting access to the clock
registers via the E
signal. At this time, the reset pin (RST) is driven active and will remain
active until V
CC
returns to nominal levels. External RAM access is inhibited in a similar
manner by forcing E
CON
to a high level. This level is within 0.2 V of the V
BAT
. E
CON
will
remain at this level as long as V
CC
remains at an out-of-tolerance condition. When V
CC
falls
below the level of the battery (V
BAT
), power input is switched from the V
CC
pin to the
SNAPHAT
®
battery and the clock registers are maintained from the attached battery supply.
External RAM is also powered by the SNAPHAT battery. All outputs except G
CON
, E
CON
,
RST
, IRQ/FT and V
OUT
, become high impedance. The V
OUT
pin is capable of supplying
100 µA of current to the attached memory with less than 0.3 V drop under this condition. On
power up, when V
CC
returns to a nominal value, write protection continues for 200 ms (max)
by inhibiting E
CON
. The RST signal also remains active during this time (see Figure 14 on
page 30).
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70°C; V
CC
= 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
M48T201Y M48T201V
Unit–70 –85
Min Max Min Max
t
AVAV
WRITE cycle time 70 85 ns
t
AVWL
Address valid to WRITE enable low 0 0 ns
t
AVEL
Address valid to chip enable low 0 0 ns
t
WLWH
WRITE enable pulse width 45 55 ns
t
ELEH
Chip enable low to chip enable high 50 60 ns
t
WHAX
WRITE enable high to address transition 0 0 ns
t
EHAX
Chip enable high to address transition 0 0 ns
t
DVWH
Input valid to WRITE enable high 25 30 ns
t
DVEH
Input valid to chip enable high 25 30 ns
t
WHDX
WRITE enable high to input transition 0 0 ns
t
EHDX
Chip enable high to input transition 0 0 ns
t
WLQZ
(2)(3)
2. C
L
= 5 pF
3. If E
goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable low to output High-Z 20 25 ns
t
AVWH
Address valid to WRITE enable high 55 65 ns
t
AVEH
Address valid to chip enable high 55 65 ns
t
WHQX
(2)(3)
WRITE enable high to output transition 5 5 ns
