Operation M48T201Y, M48T201V
16/37
Note: Most low power SRAMs on the market today can be used with the M48T201Y/V
TIMEKEEPER
®
SUPERVISOR. There are, however some criteria which should be used in
making the final choice of an SRAM to use.
The SRAM must be designed in a way where the chip enable input disables all other inputs
to the SRAM. This allows inputs to the M48T201Y/V and SRAMs to be “Don't care” once
V
CC
falls below V
PFD
(min). The SRAM should also guarantee data retention down to
V
CC
= 2.0 V. The chip enable access time must be sufficient to meet the system needs with
the chip enable (and output enable) output propagation delays included.
M48T201Y, M48T201V Clock operation
17/37
3 Clock operation
3.1 TIMEKEEPER
®
registers
The M48T201Y/V offers 16 internal registers which contain TIMEKEEPER
®
, alarm,
watchdog, flag, and control data (see Table5 on page18). These registers are memory
locations which contain external (user accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of
the incremented internal copy. TIMEKEEPER and alarm registers store data in BCD.
control, watchdog and flags (bits D0 to D3) registers store data in binary format.
3.2 Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent
reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are only data
registers and not the actual clock counters, so updating the registers can be halted without
disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating occurs approximately 1 second after the READ bit is reset to a
'0.'
3.3 Setting the clock
Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 18).
Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FFFFh-
7FFF9h, 7FFF1h) to the actual TIMEKEEPER counters and allows normal operation to
resume. After the WRITE bit is reset, the next clock update will occur approximately one
second later.
Note: Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset
to '0.'
3.4 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within the seconds register (7FFF9h). Setting it to
a '1' stops the oscillator. When reset to a '0,' the M48T201Y/V oscillator starts within one
second.
Clock operation M48T201Y, M48T201V
18/37
Note: It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
Table 5. TIMEKEEPER
®
register map
Keys:
S = Sign bit
FT = Frequency test bit
R = READ bit
W = WRITE bit
ST = Stop bit
0 = Must be set to '0'
WDS = Watchdog steering bit
AF = Alarm flag
BL = Battery low flag
SQWE = Square wave enable bit
BMB0-BMB4 = Watchdog multiplier bits
RB0-RB1 = Watchdog resolution bits
AFE = Alarm flag enable flag
ABE = Alarm in battery backup mode enable bit
RPT1-RPT5 = Alarm repeat mode bits
WDF = Watchdog flag
RS0-RS3 = SQW frequency
Address
Data
Function/range
BCD format
D7 D6 D5 D4 D3 D2 D1 D0
7FFFFh 10 years Year Year 00-99
7FFFEh 0 0 0 10 M Month Month 01-12
7FFFDh 0 0 10 date Date: Day of month Date 01-31
7FFFCh 0 FT 0 0 0 Day Day 01-07
7FFFBh 0 0 10 hours Hours (24-hour format) Hours 00-23
7FFFAh 0 10 minutes Minutes Minutes 00-59
7FFF9h ST 10 seconds Seconds Seconds 00-59
7FFF8h W R S Calibration Control
7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
7FFF6h AFE SQWE ABE Al.10M Alarm month Al. month 01-12
7FFF5h RPT4 RPT5 Al. 10 date Alarm date Al. date 01-31
7FFF4h RPT3 0 Al. 10 hours Alarm hours Al. hours 00-23
7FFF3h RPT2 Alarm 10 minutes Alarm minutes Al. minutes 00-59
7FFF2h RPT1 Alarm 10 seconds Alarm seconds Al. seconds 00-59
7FFF1h 1000 years 100 years Century 00-99
7FFF0h WDF AF 0 BL RS3 RS2 RS1 RS0 Flags

M48T201V-85MH1F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Supervisory Circuits SRAM TK Controller
Lifecycle:
New from this manufacturer.
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