Table 11: Input Switching Conditions – Command and Address (Continued)
Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 Units
Input low DC voltage: Logic 0 V
IL(DC90)min
–90 –90 mV
Table 12: Input Switching Conditions – DQ and DM
Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 Units
Input high AC voltage: Logic 1 V
IH(AC160)min
160
–
mV
Input high AC voltage: Logic 1 V
IH(AC135)min
135 135 mV
Input high DC voltage: Logic 1 V
IH(DC90)min
90 90 mV
Input low AC voltage: Logic 0 V
IL(AC160)min
–160
–
mV
Input low AC voltage: Logic 0 V
IL(AC135)min
–135 –135 mV
Input low DC voltage: Logic 0 V
IL(DC90)min
–90 –90 mV
Table 13: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition Symbol Min Max Units
Differential input logic high – slew V
IH,diff(AC)slew
180 N/A mV
Differential input logic low – slew V
IL,diff(AC)slew
N/A –180 mV
Differential input logic high V
IH,diff(AC)
2 × (V
IH(AC)
- V
REF
) V
DD
/V
DDQ
mV
Differential input logic low V
IL,diff(AC)
V
SS
/V
SSQ
2 × (V
REF
- V
IL(AC)
) mV
Single-ended high level for strobes V
SEH
V
DDQ
/2 + 160 V
DDQ
mV
Single-ended high level for CK, CK# V
DD
/2 + 160 V
DD
mV
Single-ended low level for strobes V
SEL
V
SSQ
V
DDQ
/2 - 160 mV
Single-ended low level for CK, CK# V
SS
V
DD
/2 - 160 mV
Table 14: Required Time
t
DVAC for CK/CK#, DQS/DQS# Differential for AC Ringback
Slew Rate (V/ns)
t
DVAC at 320mV (ps)
t
DVAC at 270mV (ps)
>4.0 70 209
4.0 53 198
3.0 47 194
2.0 35 186
1.8 31 184
1.6 26 181
1.4 20 177
1.2 12 171
1.0 0 164
<1.0 0 164
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN
16
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