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MT41K256M8HX-187E:D

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
Table 27: Required Time
t
VAC Above V
IH(AC)
(Below V
IL(AC)
) for Valid DQTransition
Slew Rate (V/ns)
t
VAC at 160mV (ps)
t
VAC at 135mV (ps)
>2.0 70 109
2.0 53 98
1.5 47 94
1.0 35 86
0.9 31 84
0.8 26 81
0.7 20 77
0.6 12 71
0.5 0 64
<0.5 0 64
Initialization
If the SDRAM is powered up and initialized for the 1.35V operating voltage range, volt-
age can be increased to the 1.5V operating range provided that:
•
Just prior to increasing the 1.35V operating voltages, no further commands are issued,
other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
•
The 1.5V operating voltages are stable prior to issuing new commands, other than
NOPs or COMMAND INHIBITs.
•
The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to
any READ command.
•
The ZQ calibration is performed.
t
ZQinit must be satisfied after the 1.5V operating vol-
tages are stable and prior to any READ command.
If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage
can be reduced to the 1.35V operation range provided that:
•
Just prior to reducing the 1.5V operating voltages, no further commands are issued,
other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
•
The 1.35V operating voltages are stable prior to issuing new commands, other than
NOPs or COMMAND INHIBITs.
•
The DLL is reset and relocked after the 1.35V operating voltages are stable and prior
to any READ command.
•
The ZQ calibration is performed.
t
ZQinit must be satisfied after the 1.35V operating
voltages are stable and prior to any READ command.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Initialization
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
V
DD
Voltage Switching
After the DDR3L DRAM is powered up and initialized, the power supply can be altered
between the DDR3L and DDR3 levels, provided the sequence in Figure 6 is maintained.
Figure 6: V
DD
Voltage Switching
(
)
(
)
(
)
(
)
CKE
R
TT
BA
(
)
(
)
(
)
(
)
CK, CK#
Command
Note 1 Note 1
(
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(
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(
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(
)
TdTc
Tg
Don’t Care
(
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(
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(
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(
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(
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t
IS
ODT
(
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(
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(
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(
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Th
t
MRD
t
MOD
(
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(
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(
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(
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MRSMRS
(
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t
MRD
t
MRD
(
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(
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(
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(
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MRS
MR0MR1
MR3
MRS
MR2
(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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Ti Tj Tk
(
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(
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(
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(
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RESET#
(
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(
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(
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(
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(
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(
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T = 500µs
(
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(
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(
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(
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(
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(
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Te
Ta
Tb Tf
(
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(
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(
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(
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ZQCL
(
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(
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(
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t
IS
Static LOW in case R
TT,nom
is enabled at time Tg, otherwise static HIGH or LOW
(
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(
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(
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(
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(
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(
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(
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t
IS
t
IS
t
XPR
(
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(
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(
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(
)
Time break
T
MIN
= 10ns
T
MIN
= 10ns
T
MIN
= 10ns
T
MIN
= 200µs
t
CKSRX
V
DD
, V
DDQ
(DDR3)
(
)
(
)
(
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(
)
t
DLLK
(
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(
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(
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(
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(
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t
ZQinit
(
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(
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(
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V
DD
, V
DDQ
(DDR3L)
(
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(
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(
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Valid
Valid
Valid
Valid
(
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Note:
1. From time point Td until Tk, NOP or DES commands must be applied between MRS and
ZQCL commands.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Initialization
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

MT41K256M8HX-187E:D

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Buy MT41K256M8HX-187E:D
Manufacturer:
Micron
Description:
IC DRAM 2G PARALLEL 78FBGA
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