LTC3867
31
3867f
APPLICATIONS INFORMATION
Figure 16. Branch Current Waveforms
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 16. Check the following in the
PC layout:
1. The INTV
CC
decoupling capacitor should be placed
immediately adjacent to the IC between the INTV
CC
pin
and PGND plane. A 1µF ceramic capacitor of the X7R
or X5R type is small enough to fit very close to the IC
to minimize the ill effects of the large current pulses
drawn to drive the bottom MOSFETs. An additional
4.7µF to 10µF of ceramic, tantalum or other very low
ESR capacitance is recommended in order to keep the
internal IC supply quiet.
2. Place the feedback divider between the + and – terminals
of COUT. Route DIFF
+
and DIFF
–
with minimum PC trace
spacing from the IC to the feedback divider.
3. Are the SENSE
+
and SENSE
–
printed circuit traces
routed together with minimum PC trace spacing? The
filter capacitors between SENSE
+
and SENSE
–
should
be as close as possible to the pins of the IC. Connect
the SENSE
+
and SENSE
–
pins to the pads of the sense
resistor as illustrated in Figure 2.
4. Do the (+) plates of C
IN
connect to the drain of the
topside MOSFET as closely as possible? This capacitor
provides the pulsed current to the MOSFET.
5. Keep the switching nodes, SW, BOOST and TG away
from sensitive small-signal nodes (SENSE
+
, SENSE
–
,
DIFF
+
, DIFF
–
, V
FB
). Ideally the SW, BOOST and TG printed
circuit traces should be routed away and separated from
the IC and especially the quiet side of the IC. Separate
the high dv/dt traces from sensitive small-signal nodes
with ground traces or ground planes.
6. Use a low impedance source such as a logic gate to
drive the MODE/PLLIN pin and keep the lead as short
as possible.
7. The 47pF to 330pF ceramic capacitor between the I
TH
pin and signal ground should be placed as close as
possible to the IC. Figure 16 illustrates all branch cur-
rents in a switching regulator. It becomes very clear
after studying the current waveforms why it is critical to
keep the high switching current paths to a small physical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a com-
mon ground path with any switched current paths. The
left half of the circuit gives rise to the noise generated
by a switching regulator. The ground terminations of
the synchronous MOSFET and Schottky diode should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP
®
compensa-
tion allows overcompensation for PC layouts which are
not optimized but this is not the recommended design
procedure.
+
R
IN
V
IN
V
OUT
C
IN
+
C
OUT
D1
SW2
SW1
L1
R
SENSE
R
L
3867 F16
BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH
