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ZL40205LDG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
HCSL
Driver
VDD_driver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
R= 50 Ohms
NC
RR
ZL40205 Data Sheet
9
Microsemi Corporation
Figure 8 - Clock Input - CML- AC Coupled
Figure 9 -
Clock Input - HCSL- AC Coupled
CMOS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
CMOS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
NC
ZL40205 Data Sheet
10
Microsemi Corporation
Figure 10 - Clock Input - AC-coupled Single-Ended
Figure 11 -
Clock Input - DC-coupled 3.3V CMOS
ZL40205 Data Sheet
11
Microsemi Corporation
3.2 Clock Outputs
LVPECL has a very low output impedance and a differential signal swing between 1V and 1.6 V. A simplified
diagram for the output stage is shown in Figure 12.The LVPECL to LVDS output termination is not shown since
there is a different device with the same inputs and LVDS outputs.
Figure 12 - Simplified Output Driver
out_p
out_n
The methods to terminate the ZL40205 LVPECL drivers are shown in the following figures.
LVPECL
Receiver
50
Ohms
50
Ohms
VDD
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
ZL40205
clk_p
clk_n
VDD - 2
Figure 13 - LVPECL Basic Output Termination
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ZL40205LDG1

Mfr. #:
Buy ZL40205LDG1
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 1:6 LVPECL Fanout Buffer w/Int. Term.
Lifecycle:
New from this manufacturer.
Delivery:
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