ZL40205 Data Sheet
6
Microsemi Corporation
3.0 Functional Description
The ZL40205 is an LVPECL clock fan out buffer with six output clock drivers capable of operating at frequencies up
to 750MHz.
The ZL40205 provides an internal input termination netwo
rk for DC and AC coupled inputs; optional input biasing
for AC coupled inputs is also provided. The ZL40205 can accept DC or AC coupled LVPECL and LVDS input
signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external
termination is also available.
The ZL40205 is designed to fan out
low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1 Clock Inputs
The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a
center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate.
A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in
Figure 3.
Receiver
clk_n
50
clk_p
Vt
50
Bias
ctrl
Figure 3 - Simplified Diagram of Input Stage
This following figures give the components values and configu
ration for the various circuits compatible with the
input stage and the use of the Vt and ctrl pins in each case.
In the following diagrams were the ctrl pin is log
ically one and the Vt pin is not connected, the Vt pin can be instead
connected to VDD with a capacitor. A capacitor can also help in Figure 4 between Vt and
VDD. This capacitor will
minimize the noise at the point between the two inter
nal termination resistors and improve the overall performance
of the device.
LVPECL
Driver
R
VDD_driver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
For 3.3 V: R= 50 Ohms
For 2.5 V: R= 22 Ohms
22 Ohms
22 Ohms
Not recommended for VDD_driver=2.5V
LVPECL
Driver
VDD_driver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
For 3.3 V: R= 150 Ohms
For 2.5 V: R= 85 Ohms
NC
RR
22 Ohms
22 Ohms
ZL40205 Data Sheet
7
Microsemi Corporation
Figure 4 - Clock Input - LVPECL - DC Coupled
Figure 5 -
Clock Input - LVPECL - AC Coupled
LVDS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
NC
LVDS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
NC
R
For VDD_driver = 3.3 V: R= 900 Ohms
For VDD_driver = 2.5 V: R = 680 Ohms
Note: R is only needed to provide a DC path for the
LVDS driver. See driver data sheet for more information.
ZL40205 Data Sheet
8
Microsemi Corporation
Figure 6 - Clock Input - LVDS - DC Coupled
Figure 7 - Clock Input - LVDS - AC Coupled

ZL40205LDG1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Buffer 1:6 LVPECL Fanout Buffer w/Int. Term.
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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