CS5372A-ISZR Datasheet CS5372A-ISZR, CS5371A-ISZR, CS5372A-ISZ | P10-P12

CS5371A CS5372A

10 DS748F3

DIGITAL CHARACTERISTICS (CONT.)

Notes: 20. MCLK is generated by the digital filter. If MCLK is disabled, the device automatically enters a power-

down state.

21. MSYNC is generated by the digital filter and is latched on MCLK falling edge, synchronization instant

) is on the next MCLK rising edge.

22. Decimated, filtered, and offset-corrected 24-bit output word from the digital filter.

Parameter Symbol Min Typ Max Unit

Master Clock Input

MCLK Frequency (Note 20)f

CLK

-2.048- MHz

MCLK Period (Note 20)t

mclk

-488- ns

MCLK Duty Cycle (Note 9)MCLK

40 - 60 %

MCLK Rise Time (Note 9)t

RISE

--50ns

MCLK Fall Time (Note 9)t

FALL

--50ns

MCLK Jitter (in-band or aliased in-band) (Note 9)MCLK

IBJ

--300ps

MCLK Jitter (out-of-band) (Note 9)MCLK

OBJ

--1ns

Master Sync Input

MSYNC Setup Time to MCLK Falling (Note 9, 21)t

mss

20 122 - ns

MSYNC Period (Note 9, 21)t

msync

40 976 - ns

MSYNC Hold Time after MCLK Falling (Note 9, 21)t

msh

20 122 - ns

MDATA Output

MDATA Output Bit Rate f

mdata

- 512 - kbits/s

MDATA Output Bit Period t

mdata

- 1953 - ns

MDATA Output One’s Density Range (Note 9)MDAT

14 - 86 %

Full-scale Output Code (Note 22)MDAT

0xA2EBE0

0x5D1420

CS5371A CS5372A

DS748F3 11

DIGITAL CHARACTERISTICS (CONT.)

MCLK

MSYNC

MDATA

TDATA

(2.048 MHz)

(512 kHz)

(256 kHz)

SYNC

MFLAG

Figure 6. System Timing Diagram

MCLK

MSYNC

(2.048 MHz)

mss

mcl k

msync

msh

MDATA

(512 kHz)

MFLAG

mdata

Figure 7. MCLK / MSYNC Timing Detail

CS5371A CS5372A

12 DS748F3

POWER SUPPLY CHARACTERISTICS

Notes: 23. All outputs unloaded. Digital inputs forced to VD or GND respectively.

24. Power supply rejection is characterized by applying a 100 mVp-p 50 Hz sine wave to each supply.

Parameter Symbol Min Typ Max Unit

Power Supply Current, CS5371A