CS5371A CS5372A
DS748F3 19
The CS5371A and CS5372A MSYNC input is
rising-edge triggered and resets the internal
MCLK counter/divider to guarantee synchro-
nous operation with other system devices.
While the MSYNC signal synchronizes the in-
ternal operation of the modulators, by default,
it does not synchronize the phase of the sine
wave from the CS4373A test DAC unless en-
abled in the digital filter TBSCFG register.
5.3 MDATA Connection
During normal operation the CS5371A and
CS5372A modulators output a ΔΣ serial bit
stream to the MDATA pin, with a one’s density
proportional to the differential amplitude of the
analog input signal. The output bit rate from
the MDATA output is a divide-by-four of the in-
put MCLK, and so is nominally 512 kHz.
The MDATA output has a 50% one’s density
for a mid-scale analog input, approximately
86% one’s density for a positive full-scale ana-
log input, and approximately 14% one’s densi-
ty for a negative full-scale analog input. One’s
density of the MDATA output is defined as the
ratio of ‘1’ bits to total bits in the serial bit
stream output; i.e. an 86% one’s density has,
on average, a ‘1’ value in 86 of every 100 out-
put data bits.
5.4 MFLAG Connection
The CS5371A and CS5372A ΔΣ modulators
have a fourth-order architecture which is con-
ditionally stable and may go into an oscillatory
condition if the analog inputs are over-ranged
more than 5% past either positive or negative
full-scale.
When an unstable condition is detected, the
modulator automatically collapses to a first-or-
der system to regain stability and then transi-
tions the MFLAG output low-to-high to signal
an error condition to the CS5376A digital filter.
The MFLAG output connects to a dedicated in-
put on the digital filter, causing an error flag to
be set in the status byte of the next output data
word.
For the modulator to recover from an unstable
condition, the analog input signal must be re-
duced to within the full-scale input range for at
least 32 MCLK cycles. If the analog input re-
mains over-ranged for an extended period, the
modulator will cycle between fourth-order and
first-order operation and the MFLAG output
will be seen to pulse.
5.5 OFST Connection
The CS5376A controls 12 general-purpose in-
put output (GPIO) pins through the digital filter
GPCFG register. These GPIO pins can be as-
signed to operate the CS5371A and CS5372A
OFST and PWDN pins.
If the OFST pin is pulled high, idle tones are
eliminated within the modulator by adding
-60 mV (channel 1 of CS5371A and CS5372A)
or -35 mV (channel 2 of CS5372A) of internal
differential offset during conversion to push
idle tones out of the measurement bandwidth.
Care should be taken to ensure external offset
voltages do not negate the internally added
differential offset, or idle tones will re-appear.
