CS5371A CS5372A
16 DS748F3
4. ANALOG SIGNALS
The CS5371A and CS5372A modulators have
differential analog inputs which are separated
into rough and fine charge differential pairs
(INR±, INF±) to maximize sampling accuracy.
Both sets of modulator inputs require a simple
differential anti-alias RC filter to ensure high-
frequency signals do not alias into the mea-
surement bandwidth.
4.1 INR±, INF± Modulator Inputs
The modulator analog inputs are separated
into differential rough and fine signals (INR±,
INF±). The positive half of the differential input
signal is connected to INR+ and INF+, while
the negative half is attached to INF- and INR-.
The INR± pins are switched-capacitor ‘rough
charge’ inputs that pre-charge the internal an-
alog sampling capacitor before it is connected
to the INF± fine input pins.
4.2 Input Impedance
The modulator inputs have a dynamic
switched-capacitor architecture and so have a
rough charge input impedance that is inversely
proportional to the input master clock frequen-
cy and the input capacitor size, [1 / (f x C)].
Internal to the modulator, the rough inputs
(INR±) pre-charge the sampling capacitor
used by the fine inputs (INF±), therefore the in-
put current to the fine inputs is typically very
low and the effective input impedance is or-
ders of magnitude above the impedance of the
rough inputs.
CS5372A
ΔΣ Modulator
INF+
INR+
INF-
INR-
INF-
INR-
INF+
INR+
VREF+
VREF-
VA+
VA-
VD
GND
MDATA1
MFLAG1
MDATA2
MFLAG2
MCLK
MSYNC
PWDN1
OFST
PWDN2
VREF
2.5 V
VA+
VA-
10 Ω
0.01μF
VD
CS5376A
Digital Filter
VDD2
GND
MDATA1
MFLAG1
MDATA2
MFLAG2
MCLK
MSYNC
GPIO
GPIO
GPIO
VA+
0.1μF 0.01μF
VD
VA-
0.1μF
20nF
C0G
20nF
C0G
680
CS3301A
CS3302A
AMPLIFIER
OUTR+
OUTF+
OUTF-
OUTR-
680
680
680
20nF
C0G
20nF
C0G
680
CS3301A
CS3302A
AMPLIFIER
OUTR+
OUTF+
OUTF-
OUTR-
680
680
680
VA+
VA+
VA-
VA-
VA+
VA+
VA-
VA-
100μF
Figure 11. Analog Signals
MCLK = 2.048 MHz
INR± Internal Input Capacitor = 20 pF
Impedance = [1 / (2.048 MHz * 20 pF)] = 24 kΩ.
CS5371A CS5372A
DS748F3 17
4.3 Anti-alias Filter
The modulator inputs are required to be band-
width limited to ensure modulator loop stability
and prevent high-frequency signals from alias-
ing into the measurement bandwidth. The use
of simple, single-pole, differential, low-pass
RC filters across the INR± and INF± inputs en-
sures high-frequency signals are rejected be-
fore they can alias into the measurement
bandwidth.
The CS3301A / CS3302A differential amplifi-
ers are designed with separate rough and fine
analog outputs (OUTR±, OUTF±) that match
the modulator rough and fine inputs (INR±,
INF±). External anti-alias series resistors and
external differential capacitors are required to
create the anti-alias RC filters.
The approximate -3 dB corner of the input anti-
alias filter is nominally set to the internal ana-
log sampling rate divided by 64, which itself is
a division by 4 of the MCLK rate.
Figure 9 on page 13 illustrates the CS5371A and
CS5372A modulator analog connections with
input anti-alias filter components. Filter com-
ponents on the rough and fine pins should be
identical values for optimum performance, with
the capacitor values a minimum of 0.02 μF.
The rough input can use either X7R- or C0G-
type capacitors, while the fine input requires
C0G-type capacitors for optimal linearity. Us-
ing X7R-type capacitors on the fine analog in-
puts will significantly degrade total harmonic
distortion performance.
4.4 Analog Differential Signals
Differential analog signals into the CS5371A
and CS5372A consist of two halves with equal
but opposite magnitude varying about a com-
mon mode voltage. A full-scale, 5 V
P-P
, differ-
ential signal centered on a -0.15 V common
mode voltage will have:
SIG+ = -0.15 V + 1.25 V = +1.1 V
SIG- = -0.15 V - 1.25 V = -1.4 V
SIG+ is +2.5 V relative to SIG-
For the opposite case:
SIG+ = -0.15 V - 1.25 V = -1.4 V
SIG- = -0.15 V + 1.25 V = +1.1 V
SIG+ is -2.5 V relative to SIG-
So the total swing for SIG+ relative to SIG- is
(+2.5 V) – (-2.5 V) = 5 V
p-p
differential. A simi-
lar calculation can be done for SIG- relative to
SIG+.
It’s important to note that a 5 V
p-p
differential
signal centered on a -0.15 V common mode
voltage never exceeds +1.1 V with respect to
ground and never drops below -1.4 V with re-
spect to ground on either half. By definition,
differential voltages are measured with re-
spect to the opposite half, not relative to
ground. A voltmeter differentially measuring
between SIG+ and SIG- in the above example
would correctly read 1.767 V
rms
, or 5 V
p-p
.
MCLK Frequency = 2.048 MHz
Sampling Frequency = MCLK / 4 = 512 kHz
-3 dB Filter Corner = Sampling Freq / 64 = 8 kHz
RC filter = 1 / [ 2π x(2xR
series
)xC
diff
] ~ 8 kHz
CS5371A CS5372A
18 DS748F3
5. DIGITAL SIGNALS
The CS5371A and CS5372A modulators are
designed to operate with the CS5376A digital
filter. The digital filter generates the modulator
clock and synchronization signals (MCLK and
MSYNC) while receiving back the modulator
one-bit ΔΣ conversion data and over-range
flag (MDATA and MFLAG).
5.1 MCLK Connection
The CS5376A digital filter generates the mas-
ter clock for CS5371A and CS5372A, typically
2.048 MHz, from a synchronous clock input
from the external system. If MCLK is disabled
during operation, the modulators will enter a
power down state after approximately 40 µS.
By default, MCLK is disabled at reset and is
enabled by writing the digital filter CONFIG
register.
MCLK must have low jitter to guarantee full an-
alog performance, requiring a crystal- or
VCXO-based system clock input to the digital
filter. Clock jitter on the digital filter CLK input
directly translates to jitter on MCLK.
5.2 MSYNC Connection
The CS5376A digital filter also provides a syn-
chronization signal to the CS5371A and
CS5372A modulators. The MSYNC signal is
automatically generated following a rising
edge received on the digital filter SYNC input.
By default, MSYNC generation is disabled at
reset and is enabled by writing the digital filter
CONFIG register.
The input SYNC signal to the CS5376A digital
filter sets a common reference time t
0
for mea-
surement events, thereby synchronizing ana-
log sampling across a measurement network.
The timing accuracy of the received SYNC sig-
nal from measurement node to measurement
node must be ±1 MCLK to maximize the
MSYNC analog sample synchronization accu-
racy.
CS5372A
ΔΣ Modulator
INF+
INR+
INF-
INR-
INF-
INR-
INF+
INR+
VREF+
VREF-
VA+
VA-
VD
GND
MDATA1
MFLAG1
MDATA2
MFLAG2
MCLK
MSYNC
PWDN1
OFST
PWDN2
VREF
2.5 V
VA+
VA-
10 Ω
0.01μF
VD
CS5376A
Digital Filter
VDD2
GND
MDATA1
MFLAG1
MDATA2
MFLAG2
MCLK
MSYNC
GPIO
GPIO
GPIO
VA+
0.1μF 0.01μF
VD
VA-
0.1μF
20nF
C0G
20nF
C0G
680
CS3301A
CS3302A
AMPLIFIER
OUTR+
OUTF+
OUTF-
OUTR-
680
680
680
20nF
C0G
20nF
C0G
680
CS3301A
CS3302A
AMPLIFIER
OUTR+
OUTF+
OUTF-
OUTR-
680
680
680
VA+
VA+
VA-
VA-
VA+
VA+
VA-
VA-
100μF
Figure 12. Digital Signals

CS5372A-ISZR

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Analog to Digital Converters - ADC LP High Performance Delta Sigma Mod.
Lifecycle:
New from this manufacturer.
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