CS5371A CS5372A
DS748F3 15
3.2 Decimated 24-bit Output
When the CS5371A and CS5372A modulator
operates with the CS5376A digital filter, the fi-
nal decimated, 24-bit, full-scale output code
range depends if digital offset correction is en-
abled. With digital offset correction enabled
within the digital filter, amplifier offset and the
modulator internal offset are removed from the
final conversion result.
3.3 Synchronization
The modulator is designed to operate synchro-
nously with other modulators in a distributed
measurement network, so a rising edge on the
MSYNC input resets the internal conversion
state machine to synchronize analog sample
timing. MSYNC is automatically generated by
the CS5376A digital filter after receiving a syn-
chronization signal from the external system,
and is chip-to-chip accurate within ± 1 MCLK
period.
3.4 Idle Tones
The CS5371A and CS5372A are delta-sigma-
type modulators and so can produce “idle
tones” in the measurement bandwidth when
the differential input signal is a steady-state
DC signal near mid-scale. Idle tones result
from low-frequency patterns in the output data
stream and appear in the measurement spec-
trum as small tones about -135 dB down from
full scale.
If the OFST pin is pulled high, idle tones are
eliminated within the modulator by adding
-60 mV (channel 1 of CS5371A and CS5372A)
or -35 mV (channel 2 of CS5372A) of internal
differential offset during conversion to push
idle tones out of the measurement bandwidth.
Care should be taken to ensure external offset
voltages do not negate the internally added
differential offset, or idle tones will re-appear.
3.5 Stability
The CS5371A and CS5372A ΔΣ modulators
have a fourth-order architecture which is con-
ditionally stable and may go into an oscillatory
condition if the analog inputs are over-ranged
more than 5% past either positive or negative
full scale.
If an unstable condition is detected, the modu-
lator collapses to a first-order system and tran-
sitions the MFLAG output low-to-high to signal
an error condition to the CS5376A digital filter.
The analog input signal must be reduced to
within the full-scale range for at least 32 MCLK
cycles for the modulator to recover from an os-
cillatory condition. If the analog input remains
over-ranged for an extended period, the mod-
ulator will cycle between fourth-order and first-
order operation and the MFLAG output will be
seen to pulse.
Table 1. 24-Bit Output Coding for the CS5371A
and CS5372A Modulator and CS5376A Digital
Filter Combination
Modulator
Differential
Analog Input
Signal
CS5376A Digital Filter
24-Bit Output Code
Offset
Corrected
-60 mV
Offset
-35 mV
Offset
> + (VREF+5%) Error Flag Possible
+ VREF 5D1420 5AD840 5BC688
0 V 000000 FDC420 FEB268
- VREF A2EBE0 A527C0 A43978
> - (VREF+5%) Error Flag Possible
