DS3882
Dual-Channel Automotive CCFL Controller
____________________________________________________________________ 13
2.0V
BRIGHT
LAMP FREQUENCY SOURCE
DPWM SOURCE
PSYNC
LSYNC
POSC
LOSC
0.5V
RESISTOR-SET
DIMMING
FREQUENCY
RESISTOR-SET
LAMP FREQUENCY
DS3882
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
PSYNC
LSYNC
POSC
LOSC
DS3882
2.0V
BRIGHT
LAMP FREQUENCY SOURCE
DPWM SOURCE
PSYNC
LSYNC
POSC
LOSC
0.5V
ANALOG
BRIGHTNESS
ANALOG
BRIGHTNESS
RESISTOR-SET
LAMP FREQUENCY
DIMMING CLOCK
(22.5Hz TO 440Hz)
DPWM SIGNAL
(22.5Hz TO 440Hz)
DS3882
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
PSYNC
LSYNC
POSC
LOSC
DS3882
BRIGHT
LAMP FREQUENCY SOURCE
DPWM RECEIVER
PSYNC
LSYNC
POSC
LOSC
RESISTOR-SET
LAMP FREQUENCY
DS3882
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
PSYNC
LSYNC
POSC
LOSC
DS3882
2.0V
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM SOURCE
PSYNC
LSYNC
POSC
LOSCN.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
0.5V
RESISTOR-SET
DIMMING FREQUENCY
DS3882
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
PSYNC
LSYNC
POSC
LOSC
DS3882
2.0V
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM SOURCE
PSYNC
LSYNC
POSC
LOSC
0.5V
ANALOG
BRIGHTNESS
ANALOG
BRIGHTNESS
LAMP CLOCK
(40kHz TO 100kHz)
DIMMING CLOCK
(22.5Hz TO 440Hz)
LAMP CLOCK
(40kHz TO 100kHz)
DPWM SIGNAL
(22.5Hz TO 440Hz)
LAMP CLOCK
(40kHz TO 100kHz)
DS3882
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
PSYNC
LSYNC
POSC
LOSC
DS3882
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
PSYNC
LSYNC
POSC
LOSC
DS3882
BRIGHT
LAMP FREQUENCY RECEIVER
DPWM RECEIVER
PSYNC
LSYNC
POSC
LOSC
DS3882
Figure 5. Frequency Configuration Options for Designs Using Multiple DS3882s
DS3882
Dual-Channel Automotive CCFL Controller
14 ____________________________________________________________________
Configuring Systems
with Multiple DS3882s
The source and receiver options for the lamp frequency
clock and DPWM signal allow multiple DS3882s to be
synchronized in systems requiring more than two
lamps. The lamp and dimming clocks can either be
generated on board the DS3882 using external resis-
tors to set the frequency, or they can be sourced by the
host system to synchronize the DS3882 to other system
resources. Figure 5 shows various multiple DS3882
configurations that allow both lamp and/or DPWM syn-
chronization for all DS3882s in the system.
DPWM Soft-Start
At the beginning of each lamp burst, the DS3882 pro-
vides a soft-start that slowly increases the MOSFET
gate-driver duty cycle (see Figure 6). This minimizes
the possibility of audible transformer noise that could
result from current surges in the transformer primary.
The soft-start length is fixed at 16 lamp cycles, but the
soft-start ramp profile is programmable through the four
soft-start profile registers (SSP1/2/3/4) and can be
adjusted to match the application. There are seven dif-
ferent driver duty cycles to select from to customize the
soft-start ramp (see Tables 5a and 5b). The available
duty cycles range from 0% to 19% in ~3% increments.
In addition, the MOSFET duty cycle from the last lamp
cycle of the previous burst can be used as part of the
soft-start ramp by using the most recent value duty cycle
code. Each programmed MOSFET gate duty cycle
repeats twice to make up the 16 soft-start lamp cycles.
1615141312111098765432
SSP1. 0-3
LAMP CURRENT
SOFT-START PROFILE REGISTER
SOFT-START
SOFT-START (EXPANDED)
22.5Hz TO 440Hz
DPWM SIGNAL
LAMP CURRENT
LAMP CYCLE
GAn/GBn
MOSFET GATE DRIVERS
PROGRAMMABLE SOFT-START PROFILE WITH INCREASING MOSFET PULSE WIDTHS OVER
A 16 LAMP CYCLE PERIOD RESULTS IN A LINEAR RAMP IN LAMP CURRENT.
SSP1. 4-7
SSP2. 0-3
SSP2. 4-7
SSP3. 0-3
SSP3. 4-7
SSP4. 0-3
SSP4. 4-7
1
Figure 6. Digital PWM Dimming and Soft-Start
Setting the Lamp and Dimming
Clock (DPWM) Frequencies
Using External Resistors
Both the lamp and dimming clock frequencies can be
set using external resistors. The resistance required for
either frequency can be determined using the following
formula:
where K = 1600kΩ kHz for lamp frequency calculations.
When calculating the resistor value for the dimming clock
frequency, K will be one of four values as determined by
the desired frequency and the POSCR0 and POSCR1 bit
settings as shown in the Control Register 2 (CR2) Table 7
in the
Detailed Register Descriptions
section.
Example: Selecting the resistor values to configure a
DS3882 to have a 50kHz lamp frequency and a 160Hz
dimming clock frequency: For this configuration,
POSCR0 and POSCR1 must be programmed to 1 and
0, respectively, to select 90Hz to 220Hz as the dimming
clock frequency range. This sets K for the dimming
clock resistor (R
POSC
) calculation to 4kΩ kHz. For the
lamp frequency resistor (R
LOSC
) calculation, K =
1600kΩ kHz, which sets the lamp frequency K value
regardless of the frequency. The formula above can
now be used to calculate the resistor values for R
LOSC
and R
POSC
as follows:
Supply Monitoring
The DS3882 has supply voltage monitors (SVMs) for
both the inverter’s transformer DC supply (V
INV
) and its
own V
CC
supply to ensure that both voltage levels are
adequate for proper operation. The transformer supply
is monitored for overvoltage conditions at the SVMH pin
and undervoltage conditions at the SVML pin. External
resistor-dividers at each SVM input feed into two com-
parators (see Figure 7), both having 2V thresholds.
Using the equation below to determine the resistor val-
ues, the SVMH and SVML trip points (V
TRIP
) can be
customized to shut off the inverter when the trans-
former’s supply voltage rises above or drops below
specified values. Operating with the transformer’s sup-
ply at too low of a level can prevent the inverter from
reaching the strike voltage and could potentially cause
numerous other problems. Operating with the trans-
former voltage at too high of a level can be damaging
to the inverter components. Proper use of the SVMs
can prevent these problems. If desired, the high and/or
low SVMs can be disabled by connecting the SVMH
pin to GND and the SVML pin to V
CC
.
The V
CC
monitor is used as a 5V supply undervoltage
lockout (UVLO) that prevents operation when the
DS3882 does not have adequate voltage for its analog
circuitry to operate or to drive the external MOSFETs.
The V
CC
monitor features hysteresis to prevent V
CC
noise from causing spurious operation when V
CC
is
near the trip point. This monitor cannot be disabled by
any means.
Fault Monitoring
The DS3882 provides extensive fault monitoring for
each channel. It can detect open-lamp, lamp overcur-
rent, failure to strike, and overvoltage conditions. The
DS3882 can be configured to disable all channels if
one or more channels enter a fault state or it can be
configured to disable only the channel where the fault
occurred. Once a fault state has been entered, the
FAULT output is asserted and the channel(s) remains
disabled until it is reset by a user or host control event.
See
Step 4, Fault Handling
for more detail. The DS3882
can also be configured to automatically attempt to clear
a detected fault (except lamp overcurrent) by re-striking
the lamp. Configuration bits for the fault monitoring
options are located in CR1 and CR2. The DS3882 also
has real-time status indicators bits located in the SR1
and SR2 register (SRAM) that assert whenever a corre-
sponding fault occurs.
V
RR
R
TRIP
.
=
+
20
12
1
R
k kHz
kHz
k
R
k kHz
kHz
k
LOSC
POSC
.
.
.
=
=
=
=
1600
50
32 0
4
0 160
25 0
Ω
Ω
Ω
Ω
R
K
f
OSC
OSC
=
DS3882
Dual-Channel Automotive CCFL Controller
____________________________________________________________________ 15
SVML
R
2
R
1
2.0V
V
INV
SVMH
R
2
V
TRIP
V
TRIP
R
1
2.0V
V
INV
DS3882
Figure 7. Setting the SVM Threshold Voltage

DS3882E+C

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Display Drivers & Controllers DualCh Automotive CCFL Controller
Lifecycle:
New from this manufacturer.
Delivery:
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