DS3882
Dual-Channel Automotive CCFL Controller
4 _____________________________________________________________________
Note 1: All voltages are referenced to ground unless otherwise noted. Currents into the IC are positive, out of the IC negative.
Note 2: During fault conditions, the AC-coupled feedback values are allowed to be below the absolute max rating of the LCM or
OVD pin for up to 1 second.
Note 3: Voltage with respect to V
DCB
.
Note 4: Lamp overdrive and analog dimming (based on reduction of lamp current) are disabled.
Note 5: This is the minimum pulse width guaranteed to generate an output burst, which generates the DS3882’s minimum burst
duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC
input is greater than the DS3882’s minimum duty cycle, the output’s duty cycle tracks the PSYNC’s duty cycle. Leaving
PSYNC low (0% duty cycle) disables the GAn and GBn outputs in DPWM receiver mode.
Note 6: This is the maximum lamp frequency duty cycle that is generated at any of the GAn or GBn outputs with spread-spectrum
modulation disabled.
Note 7: I
2
C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I
2
C stan-
dard-mode timing.
Note 8: After this period, the first clock pulse can be generated.
Note 9: C
B
—total capacitance allowed on one bus line in picofarads.
Note 10: EEPROM write time applies to all the EEPROM memory. EEPROM write begins after a stop condition occurs.
Note 11: Guaranteed by design.
I
2
C AC ELECTRICAL CHARACTERISTICS (See Figure 9)
(V
CC
= +4.75V to +5.25V, T
A
= -40°C to +105°C, timing referenced to V
IL(MAX)
and V
IH(MIN)
.)
