DS3882
Dual-Channel Automotive CCFL Controller
____________________________________________________________________ 19
Table 2. Status Register 1 (SR1) [SRAM, E0h]
BIT R/W
POWER-UP
DEFAULT
NAME FUNCTION
0 R 0 FAULT_RT
Fault Condition—Real Time. A real-time bit that indicates the current operating status of
channel 1.
0 = Normal condition
1 = Fault condition
1 R 0 FAULT_L
Fault Condition—Latched. A latched bit that is set when the channel enters a fault
condition. This bit is cleared when read, regardless of the current state of fault.
2 R 0 STO_L
Lamp Strike Timeout—Latched. A latched bit that is set when the lamp fails to strike.
This bit is cleared when read.
3 R 0 OV_L
Overvoltage—Latched. A latched bit that is set when a lamp overvoltage is present for
at least 64 lamp cycles. This bit is cleared when read.
4 R 0 LOUT_L
Lamp Out—Latched. A latched bit that is set when a lamp out is detected. This bit is
cleared when read.
5 R 0 LOC_L
Lamp Overcurrent—Latched. A latched bit that is set when a lamp overcurrent is
detected. This bit is cleared when read.
6 R 0 SVML_RT
Supply Voltage Monitor Low—Real Time. A real-time bit that reports the comparator
output of the SVML pin.
7 R 0 SVMH_RT
Supply Voltage Monitor High—Real Time. A real-time bit that reports the comparator
output of the SVMH pin.
Note 1: Writing to this register has no effect on it.
Note 2: See Figure 8 for more details on how the status bits are set.
Note 3: SR1 is cleared when any of the following occurs:
V
CC
drops below the UVLO threshold
the SVML or SVMH thresholds are crossed
the PDN hardware pin goes high
the PDNE software bit is written to a logic 1
the channel is disabled by the CH1D control bit
DS3882
Dual-Channel Automotive CCFL Controller
20 ____________________________________________________________________
Table 3. Status Register 2 (SR2) [SRAM, E1h]
BIT R/W
POWER-UP
DEFAULT
NAME FUNCTION
0 R 0 FAULT_RT
Fault Condition—Real Time. A real-time bit that indicates the current operating status
of channel 2.
0 = Normal condition
1 = Fault condition
1 R 0 FAULT_L
Fault Condition—Latched. A latched bit that is set when the channel enters a fault
condition. This bit is cleared when read regardless of the current state of fault.
2 R 0 STO_L
Lamp Strike Time Out—Latched. A latched bit that is set when the lamp fails to strike.
This bit is cleared when read.
3 R 0 OV_L
Overvoltage—Latched. A latched bit that is set when a lamp overvoltage is present
for at least 64 lamp cycles. This bit is cleared when read.
4 R 0 LOUT_L
Lamp Out—Latched. A latched bit that is set when a lamp out is detected. This bit is
cleared when read.
5 R 0 LOC_L
Lamp Overcurrent—Latched. A latched bit that is set when a lamp overcurrent is
detected. This bit is cleared when read.
6 R 0 RSVD Reserved. Could be either 0 or 1 when read.
7 R 0 RSVD Reserved. Could be either 0 or 1 when read.
Note 1: Writing to this register has no effect on it.
Note 2: See Figure 8 for more details on how the status bits are set.
Note 3: SR2 is cleared when any of the following occurs:
V
CC
drops below the UVLO threshold
the SVML or SVMH thresholds are crossed
the PDN hardware pin goes high
the PDNE software bit is written to a logic 1
the channel is disabled by the CH2D control bit
Table 4. Brightness Lamp Current Register (BLC) [SRAM, E3h]
BIT R/W
FACTORY
DEFAULT
NAME FUNCTION
0 R/W 0 LC0
1 R/W 0 LC1
2 R/W 0 LC2
3 R/W 0 LC3
4 R/W 0 LC4
These five control bits determine the target value for the lamp current. 11111b is
35% of the nominal level and 00000b is 100% of the nominal level. These control
bits are used for fine adjustment of the lamp brightness.
5 R/W 0 CH1D
Channel 1 Disable
0 = Channel 1 enabled
1 = Channel 1 disabled
6 R/W 0 CH2D
Channel 2 Disable. Useful for dimming in two lamp applications.
0 = Channel 2 enabled
1 = Channel 2 disabled
7 R/W 0 SEEB
SRAM-Shadowed EEPROM Write Control
0 = Enables writes to EEPROM
1 = Disables writes to EEPROM
DS3882
Dual-Channel Automotive CCFL Controller
____________________________________________________________________ 21
Table 5a. Soft-Start Protocol Registers (SSPx) [Shadowed-EEPROM, F0h, F1h, F2h, F3h]
MSB LSB
SSP# ADDR
FACTORY
DEFAULT
7 654 3 2 1 0
SSP1 F0h 21h LST1 Lamp Cycles 3 and 4 LST0 Lamp Cycles 1 and 2
SSP2 F1h 43h RSVD Lamp Cycles 7 and 8 RSVD Lamp Cycles 5 and 6
SSP3 F2h 65h RSVD Lamp Cycles 11 and 12 RSVD Lamp Cycles 9 and 10
SSP4 F3h 77h RSVD Lamp Cycles 15 and 16 RSVD Lamp Cycles 13 and 14
Table 5b. MOSFET Duty Cycle (MDC)Codes for Soft-Start Settings
BIT R/W NAME FUNCTION
0 R/W MDC0
MDC0/1/2: These bits determine a MOSFET duty cycle that will repeat twice in the
16 lamp cycle soft-start.
1 R/W MDC1
MDC CODE MOSFET DUTY CYCLE MDC CODE MOSFET DUTY CYCLE
0h Fixed at 0% 4h Fixed at 13%
2 R/W MDC2
1h Fixed at 3% 5h Fixed at 16%
2h Fixed at 6% 6h Fixed at 19%
3h Fixed at 9% 7h Most Recent Value
3 R/W LST0 / RSVD
4 R/W MDC0
LST0/1: These bits select strike and lamp-out timeout. LST0 and LST1
control fault behavior for all lamps.
5 R/W MDC1 LST1 LST0
STRIKE AND LAMP-OUT TIMEOUT
(LAMP FREQUENCY CYCLES)
EXAMPLE TIMEOUT IF
LAMP FREQUENCY IS 50kHz
0 0 32,768 0.66 Seconds
6 R/W MDC2
0 1 65,536 1.31 Seconds
1 0 98,304 1.97 Seconds
7 R/W LST1 / RSVD
1 1 Reserved

DS3882E+C

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Display Drivers & Controllers DualCh Automotive CCFL Controller
Lifecycle:
New from this manufacturer.
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