AD9398
Rev. 0 | Page 9 of 44
DESIGN GUIDE
GENERAL DESCRIPTION
The AD9398 is a fully integrated solution for receiving
DVI/HDMI signals and is capable of decoding HDCP-
encrypted signals through connections to an external
EEPROM. The circuit is ideal for providing an interface for
HDTV monitors or as the front end to high performance video
scan converters.
Implemented in a high performance CMOS process, the
interface can capture signals with pixel rates of up to 150 MHz.
The AD9398 includes all necessary circuitry for decoding
TMDS signaling including those encrypted with HDCP.
Included in the output formatting is a color space converter
(CSC), which accommodates any input color space and can
output any color space. All controls are programmable via a 2-
wire serial interface. Full integration of these sensitive mixed
signal functions makes system design straight-forward and less
sensitive to the physical and electrical environments.
DIGITAL INPUTS
The digital control inputs (I
2
C) on the AD9398 operate to 3.3 V
CMOS levels. In addition, all digital inputs, except the TMDS
(HDMI/DVI) inputs, are 5 V tolerant (applying 5 V to them
does not cause damage.) The TMDS input pairs (Rx0+/Rx0−,
Rx1+/Rx1−, Rx2+/Rx2−, and RxC+/RxC−) must maintain a
100 Ω differential impedance (through proper PCB layout)
from the connector to the input where they are internally
terminated (50 Ω to 3.3 V). If additional ESD protection is
desired, use of a California Micro Devices (CMD) CM1213
(among others) series low capacitance ESD protection offers 8
kV of protection to the HDMI TMDS lines.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic. However, it is
tolerant of 5 V logic signals.
OUTPUT SIGNAL HANDLING
The digital outputs operate from 1.8 V to 3.3 V (V
DD
).
POWER MANAGEMENT
The AD9398 uses the activity detect circuits, the active interface
bits in the serial bus, the active interface override bits, the
power-down bit, and the power-down pin to determine the
correct power state. There are four power states: full power, seek
mode, auto power-down, and power-down.
Table 7 summarizes
how the AD9398 determines the power mode to use and which
circuitry is powered on/off in each of these modes. The power-
down command has priority and then the automatic circuitry.
The power-down pin (Pin 81—polarity set by Register 0x26[3])
can drive the chip into four power-down options. Bit 2 and Bit 1
of Register 0x26 control these four options. Bit 0 controls
whether the chip is powered down or the outputs are placed in
high impedance mode (with the exception of SOG). Bit 7 to
Bit 4 of Register 0x26 control whether the outputs, SOG, Sony
Philips digital interface (SPDIF ) or Inter-IC sound bus (I
2
S or
IIS) outputs are in high impedance mode. See the
2-Wire Serial
Control Register Detail
section for the details.
Table 7. Power-Down Mode Descriptions
Inputs
Mode Power-Down
1
Sync Detect
2
Auto PD Enable
3
Power-On or Comments
Full Power 1 1 X Everything
Seek Mode 1 0 0 Everything
Seek Mode 1 0 1 Serial bus, sync activity detect, SOG, band gap reference
Power-Down 0 X Serial bus, sync activity detect, SOG, band gap reference
1
Power-down is controlled via Bit 0 in Serial Bus Register 0x26.
2
Sync detect is determined by OR’ing Bit 7 to Bit 2 in Serial Bus Register 0x15.
3
Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27.
AD9398
Rev. 0 | Page 10 of 44
TIMING
The output data clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.
Figure 3 shows the timing operation of the AD9398.
t
PER
t
DCYCLE
t
SKEW
DATAC
K
05678-003
DATA
HSOUT
Figure 3. Output Timing
VSYNC FILTER AND ODD/EVEN FIELDS
The VSYNC filter is used to eliminate spurious VSYNCs, maintain
a consistent timing relationship between the VSYNC and
HSYNC output signals, and generate the odd/even field output.
The filter works by examining the placement of VSYNC
with respect to HSYNC and, if necessary, slightly shifting
it in time at the VSOUT output. The goal is to keep the
VSYNC and HSYNC leading edges from switching at the
same time, eliminating confusion as to when the first line
of a frame occurs. Enabling the VSYNC filter is done with
Register 0x21[5]. Use of the VSYNC filter is recommended for
all cases, including interlaced video, and is required when using
the HSYNC per VSYNC counter.
Figure 4 and Figure 5
illustrate even/odd field determination in two situations.
FIELD 1 FIELD 0
SYNC SEPARATOR THRESHOLD
FIELD 1 FIELD 0
23 21431
HSIN
VSIN
4
VSOUT
O/E FIELD
EVEN FIELD
QUADRAN
T
05678-004
Figure 4. VSYNC Filter—Even
FIELD 1 FIELD 0
SYNC SEPARATOR THRESHOLD
FIELD 1 FIELD 0
23 214431
HSIN
VSIN
VSOUT
O/E FIELD
ODD FIELD
QUADRAN
T
05678-005
Figure 5. VSYNC Filter—Odd
HDMI RECEIVER
The HDMI receiver section of the AD9398 allows the reception
of a digital video stream, which is backward compatible with
DVI and able to accommodate not only video of various for-
mats (RGB, YCrCb 4:4:4, 4:2:2), but also up to eight channels of
audio. Infoframes are transmitted carrying information about
the video format, audio clocks, and many other items necessary
for a monitor to use fully the information stream available.
The earlier digital visual interface (DVI) format was restricted
to an RGB 24-bit color space only. Embedded in this data
stream were HSYNCs, VSYNCs, and display enable (DE)
signals, but no audio information. The HDMI specification
allows transmission of all the DVI capabilities, but adds several
YCrCb formats that make the inclusion of a programmable
color space converter (CSC) a very desirable feature. With this,
the scaler following the AD9398 can specify that it always
wishes to receive a particular format—for instance, 4:2:2 YCrCb—
regardless of the transmitted mode. If RGB is sent, the CSC can
easily convert that to 4:2:2 YCrCb while relieving the scaler of
this task.
In addition, the HDMI specification supports the transmission
of up to eight channels of S/PDIF or I
2
S audio. The audio
information is packetized and transmitted during the video
blanking periods along with specific information about the
clock frequency. Part of this audio information (audio
infoframe) tells the user how many channels of audio are being
transmitted, where they should be placed, information
regarding the source (make, model), and other data.
DE GENERATOR
The AD9398 has an on-board generator for DE, for start of
active video (SAV), and for end of active video (EAV), all of
which are necessary for describing the complete data stream for
a BT656-compatible output. In addition to this particular
output, it is possible to generate the DE for cases in which a
scaler is not used. This signal alerts the following circuitry as to
which are displayable video pixels.
AD9398
Rev. 0 | Page 11 of 44
4:4:4 TO 4:2:2 FILTER
The AD9398 contains a filter that allows it to convert a signal
from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the
maximum accuracy and fidelity of the original signal.
Input Color Space to Output Color Space
The AD9398 can accept a wide variety of input formats and
either retain that format or convert to another. Input formats
supported are:
4:4:4 YCrCb 8-bit
4:2:2 YCrCb 8-, 10-, and 12-bit
RGB 8-bit
Output modes supported are:
4:4:4 YCrCb 8-bit
4:2:2 YCrCb 8-, 10-, and 12-bit
Dual 4:2:2 YCrCb 8-bit
Color Space Conversion (CSC) Matrix
The CSC matrix in the AD9398 consists of three identical
processing channels. In each channel, three input values are
multiplied by three separate coefficients. Also included are an
offset value for each row of the matrix and a scaling multiple for
all values. Each value has a 13-bit, twos complement resolution
to ensure the signal integrity is maintained. The CSC is
designed to run at speeds up to 150 MHz, supporting
resolutions up to 1080p at 60 Hz. With any-to-any color space
support, formats such as RGB, YUV, YCbCr, and others are
supported by the CSC.
The main inputs, R
IN
, G
IN
, and B
IN
come from the 8- to 12-bit
inputs from each channel. These inputs are based on the input
format detailed in
Table 10. The mapping of these inputs to the
CSC inputs is shown in
Table 8.
Table 8. CSC Port Mapping
Input Channel CSC Input Channel
R/CR R
IN
Gr/Y G
IN
B/CB BB
IN
One of the three channels is represented in
Figure 6. In each
processing channel, the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
−0.9998 to +0.9998. The variable labeled a4 is used as an offset
control. The CSC_Mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2
CSC_Mode
.
The functional diagram for a single channel of the CSC, as
shown in
Figure 6, is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
05678-006
×2
2
1
0
×
×
×
a1[12:0]
a2[12:0]
a3[12:0]
R
IN
[11:0]
G
IN
[11:0]
B
IN
[11:0]
+
×4
CSC_Mode[1:0]
a4[12:0]
R
OUT
[11:0]
+
1
4096
×
1
4096
×
1
4096
×
+
Figure 6. Single CSC Channel
A programming example and register settings for several
common conversions are listed in the
Color Space Converter
(CSC) Common Settings
section.
For a detailed functional description and more programming
examples, refer to Application Note AN-795, AD9880 Color
Space Converter User's Guide.

AD9398/PCBZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
BOARD EVALUATION FOR AD9398
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet