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AD9398/PCBZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
AD9398
Rev. 0 | Page 30 of 44
0x40—Bits[7:0] CSC B2 LSBs
0x41—Bits[4:0] CSC B3 MSBs
The default value for the 13-bit B3 is 0x1E89.
0x42—Bits[7:0] CSC B3 LSBs
0x43—Bits[4:0] CSC B4 MSBs
The default value for the 13-bit B4 is 0x0291.
0x44—Bits[7:0] CSC B4 LSBs
0x45—Bits[4:0] CSC C1 MSBs
The default value for the 13-bit C1 is 0x0000.
0x46—Bit[7:0] CSC C1 LSBs
0x47—Bit[4:0] CSC C2 MSBs
The default value for the 13 bit C2 is 0x0800.
0x48—Bits[7:0] CSC C2 LSBs
0x49—Bits[4:0] CSC C3 MSBs
The default value for the 13-bit C3 is 0x0E87.
0x4A—Bits[7:0] CSC C3 LSBs
0x4B—Bits[4:0] CSC C4 MSBs
The default value for the 13-bit C4 is 0x18BD.
0x4C—Bits[7:0] CSC C4 LSBs
0x57—Bit[7] AV Mute Override
0x57—Bit[6] AV Mute Value
0x57—Bit[3] Disable AV Mute
0x57—Bit[2] Disable Audio Mute
0x58—Bit[7] MCLK PLL Enable
This bit enables the use of the analog PLL.
0x58—Bits[6:4] MCLK PLL_N
These bits control the division of the MCLK out of the PLL.
Table 18.
PLL_N [2:0] MCLK Divide Value
0 /1
1 /2
2 /3
3 /4
4 /5
5 /6
6 /7
7 /8
0x58—Bit[3] N_CTS_Disable
This bit makes it possible to prevent the N/CTS packet on the
link from writing to the N and CTS registers.
0x58—Bits[2:0] MCLK f
S
_N
These bits control the multiple of 128 f
S
used for MCLK out.
Table 19.
MCLK f
S
_N [2:0] f
S
Multiple
0 128
1 256
2 384
3 512
4 640
5 768
6 896
7 1024
0x59—Bit[6] MDA/MCL PU Disable
This bit disables the inter-MDA/MCL pull-ups.
0x59—Bit[5] CLK Term O/R
This bit allows for overriding during power down.
0 = auto, 1 = manual.
0x59—Bit[4] Manual CLK Term
This bit allows normal clock termination or disconnects this.
0 = normal, 1 = disconnected.
0x59—Bit[2] FIFO Reset UF
This bit resets the audio FIFO if underflow is detected.
0x59—Bit[1] FIFO Reset OF
This bit resets the audio FIFO if overflow is detected.
0x59—Bit[0] MDA/MCL Three-State
This bit three-states the MDA/MCL lines to allow in-circuit
programming of the EEPROM.
0x5A—Bits[6:0] Packet Detect
This register indicates if a data packet in specific sections has
been detected. These seven bits are updated if any specific
packet has been received since last reset or loss of clock detect.
Normal is 0x00.
Table 20.
Packet Detect Bit Packet Detected
0 AVI infoframe
1 Audio infoframe
2 SPD infoframe
3 MPEG source infoframe
4 ACP packets
5 ISRC1 packets
6 ISRC2 packets
0x5B—Bit[3] HDMI Mode
0 = DVI, 1 = HDMI.
AD9398
Rev. 0 | Page 31 of 44
0x5E—Bits[7:6] Channel Status Mode
0x5E—Bits[5:3] PCM Audio Data
0x5E—Bit[2] Copyright Information
0x5E—Bit[1] Linear PCM Identification
0x5E—Bit[0] Use of Channel Status Block
0x5F—Bits[7:0] Channel Status Category Code
0x60—Bits[7:4] Channel Number
0x60—Bits[3:0] Source Number
0x61—Bits[5:4] Clock Accuracy
0x61—Bits[3:0] Sampling Frequency
Table 21.
Code Frequency (kHz)
0x0 44.1
0x2 48
0x3 32
0x8 88.2
0xA 96
0xC 176.4
0xE 192
0x62—Bits[3:0] Word Length
0x7B—Bits[7:0] CTS (Cycle Time Stamp) (19:12)
These are the most significant 8 bits of a 20-bit word used in the
20-bit N term in the regeneration of the audio clock.
0x7C—Bits[7:0] CTS (11:4)
0x7D—Bits[7:4] CTS (3:0)
0x7D—Bits[3:0] N (19:16)
These are the most significant 4 bits of a 20-bit word used along
with the 20-bit CTS term to regenerate the audio clock.
0x80—AVI Infoframe Version
0x81—Bits[6:5] Y[1:0]
This register indicates whether data is RGB, 4:4:4, or 4:2:2.
Table 22.
Y Video Data
00 RGB
01 YCbCr 4:2:2
10 YCbCr 4:4:4
0x81—Bit[4] Active Format Information Present
0 = no data.1 = active format information valid.
0x81—Bits[3:2] Bar Information
Table 23.
B Bar Type
00 No bar information
01 Horizontal bar information valid
10 Vertical bar information valid
11 Horizontal and vertical bar information valid
0x81—Bits[1:0] Scan Information
Table 24.
S [1:0] Scan Type
00 No information
01 Overscanned (television)
10 Underscanned (computer)
0x82—Bits[7:6] Colorimetry
Table 25.
C [1:0] Colorimetry
00 No data
01 SMPTE 170M, ITU601
10 ITU 709
0x82—Bits[5:4] Picture Aspect Ratio
Table 26.
M[1:0] Aspect Ratio
00 No data
01 4:3
10 16:9
0x82—Bits[3:0] Active Format Aspect Ratio
Table 27.
R [3:0] Active Format A/R
0x8 Same as picture aspect ratio (M [1:0])
0x9 4:3 (center)
0xA 16:9 (center)
0xB 14:9 (center)
0x83—Bits[1:0] Nonuniform Picture Scaling
Table 28.
SC [1:0] Picture Scaling
00 No known nonuniform scaling
01 Has been scaled horizontally
10 Has been scaled vertically
11 Has been scaled both horizontally and vertically
0x84—Bits[6:0] Video ID Code
See CEA EDID short video descriptors.
0x85—Bits[3:0] Pixel Repeat
This value indicates how many times the pixel was repeated. 0x0
= no repeats, sent once, 0x8 = 8 repeats, sent 9 times, and so on.
0x86—Bits[7:0] Active Line Start LSB
Combined with the MSB in Register 0x88, these bits indicate
the beginning line of active video. All lines before this comprise
a top horizontal bar. This is used in letter box modes. If the 2-
byte value is 0x00, there is no horizontal bar.
AD9398
Rev. 0 | Page 32 of 44
0x87—Bit[6:0] New Data Flags (NDF)
This register indicates whether data in specific sections has
changed. In the address space from 0x80 to 0xFF, each register
address ending in 0b111 (for example, 0x87, 0x8F, 0x97, 0xAF)
is an NDF register. They all have the same data and all are reset
upon reading any one of them.
Table 29.
NDF Bit Number Changes Occurred
0 AVI infoframe
1 Audio infoframe
2 SPD infoframe
3 MPEG source infoframe
4 ACP packets
5 ISRC1 packets
6 ISRC2 packets
0x88—Bits[7:0] Active Line Start MSB
See Register 0x86.
0x89—Bits[7:0] Active Line End LSB
Combined with the MSB in Register 0x8A these bits indicate
the last line of active video. All lines past this comprise a lower
horizontal bar. This is used in letter-box modes. If the 2-byte
value is greater than the number of lines in the display, there is
no lower horizontal bar.
0x8A—Bits[7:0] Active Line End MSB
See Register 0x89.
0x8B—Bits[7:0] Active Pixel Start LSB
Combined with the MSB in Register 0x8C, these bits indicate
the first pixel in the display which is active video. All pixels
before this comprise a left vertical bar. If the 2-byte value is
0x00, there is no left bar.
0x8C—Bits[7:0] Active Pixel Start MSB
See Register 0x8B.
0x8D—Bits[7:0] Active Pixel End LSB
Combined with the MSB in Register 0x8E, these bits indicate
the last active video pixel in the display. All pixels past this
comprise a right vertical bar. If the 2-byte value is greater than
the number of pixels in the display, there is no vertical bar.
0x8E—Bits[7:0] Active Pixel End MSB
See Register 0x8D.
0x8F—Bits[6:0] NDF
See Register 0x87.
0x90—Bits[7:0] Audio Infoframe Version
0x91—Bits[7:4] Audio Coding Type
These bits identify the audio coding so that the receiver may
process audio properly.
Table 30.
CT [3:0] Audio Coding
0x0 Refer to stream header
0x1 IEC60958 PCM
0x2 AC-3
0x3 MPEG1 (Layers 1 and 2)
0x4 MP3 (MPEG1 Layer 3)
0x5 MPEG2 (multichannel)
0x6 AAC
0x7 DTS
0x8 ATRAC
0x91—Bits[2:0] Audio Channel Count
These bits specify how many audio channels are being sent—
2 channels to 8 channels.
Table 31.
CC [2:0] Channel Count
000 Refer to stream header
001 2
010 3
011 4
100 5
101 6
110 7
111 8
0x92—Bits[4:2] Sampling Frequency
0x92—Bits[1:0] Ample Size
0x93—Bits[7:0] Max Bit Rate
For compressed audio only, when this value is multiplied by
8 kHz, it represents the maximum bit rate. A value of 0x08 in
this field yields a maximum bit rate of (8 kHz × 8 kHz = 64 kHz).
0x94—Bits[7:0] Speaker Mapping
These bits define the suggested placement of speakers.
Table 32.
Abbreviation Speaker Placement
FL Front left
FC Front center
FR Front right
FCL Front center left
FCR Front center right
RL Rear left
RC Rear center
RR Rear right
RCL Rear center left
RCR Rear center right
LFE Low frequency effect
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

AD9398/PCBZ

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Buy AD9398/PCBZ
Manufacturer:
Analog Devices Inc.
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BOARD EVALUATION FOR AD9398
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