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AD9398/PCBZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
AD9398
Rev. 0 | Page 24 of 44
Hex Address
Read/Write
or Read
Only
Bits
Default
Value
Register Name Description
0xC8 7 ISRC1 Continued
International standard recording code (ISRC1).
continued. This indicates an ISRC2 packet is being
transmitted.
Read 6 ISRC1 Valid 0 = ISRC1 status bits and PBs not valid.
1 = ISRC1 status bits and PBs valid.
001 = starting position.
[2:0] ISRC1 Status 010 = intermediate position.
100 = final position.
0xC9 Read [7:0] ISRC1 Packet Byte 0 ISRC1 Packet Byte 0 (ISRC1_PB0).
0xCA Read [7:0] ISRC1_PB1 ISRC1_PB1.
0xCB Read [7:0] ISRC1_PB2 ISRC1_PB2.
0xCC Read [7:0] ISRC1_PB3 ISRC1_PB3.
0xCD Read [7:0] ISRC1_PB4 ISRC1_PB4.
0xCE Read [7:0] ISRC1_PB5 ISRC1_PB5.
0xCF Read [6:0] NDF New data flags (see 0x87).
0xD0 Read [7:0] ISRC1_PB6 ISRC1_PB6.
0xD1 Read [7:0] ISRC1_PB7 ISRC1_PB7.
0xD2 Read [7:0] ISRC1_PB8 ISRC1_PB8.
0xD3 Read [7:0] ISRC1_PB9 ISRC1_PB9.
0xD4 Read [7:0] ISRC1_PB10 ISRC1_PB10.
0xD5 Read [7:0] ISRC1_PB11 ISRC1_PB11.
0xD6 Read [7:0] ISRC1_PB12 ISRC1_PB12.
0xD7 Read [6:0] NDF New data flags (see 0x87).
0xD8 Read [7:0] ISRC1_PB13 ISRC1_PB13.
0xD9 Read [7:0] ISRC1_PB14 ISRC1_PB14.
0xDA Read [7:0] ISRC1_PB15 ISRC1_PB15.
0xDB Read [7:0] ISRC1_PB16 ISRC1_PB16.
0xDC Read [7:0] ISRC2 Packet Byte 0
ISRC2 Packet Byte 0 (ISRC2_PB0). This is transmitted only
when the ISRC_ continue bit (Register 0xC8, Bit 7) is set
to 1.
0xDD Read [7:0] ISRC2_PB1 ISRC2_PB1.
0xDE Read [7:0] ISRC2_PB2 ISRC2_PB2.
0xDF Read [6:0] New Data Flags New data flags (see 0x87).
0xE0 Read [7:0] ISRC2_PB3 ISRC2_PB3.
0xE1 Read [7:0] ISRC2_PB4 ISRC2_PB4.
0xE2 Read [7:0] ISRC2_PB5 ISRC2_PB5.
0xE3 Read [7:0] ISRC2_PB6 ISRC2_PB6.
0xE4 Read [7:0] ISRC2_PB7 ISRC2_PB7.
0xE5 Read [7:0] ISRC2_PB8 ISRC2_PB8.
0xE6 Read [7:0] ISRC2_PB9 ISRC2_PB9.
0xE7 Read [6:0] New Data Flags New data flags (see 0x87).
0xE8 Read [7:0] ISRC2_PB10 ISRC2_PB10.
0xE9 Read [7:0] ISRC2_PB11 ISRC2_PB11.
0xEA Read [7:0] ISRC2_PB12 ISRC2_PB12.
0xEB Read [7:0] ISRC2_PB13 ISRC2_PB13.
0xEC Read [7:0] ISRC2_PB14 ISRC2_PB14.
0xED Read [7:0] ISRC2_PB15 ISRC2_PB15.
0xEE Read [7:0] ISRC2_PB16 ISRC2_PB16.
AD9398
Rev. 0 | Page 25 of 44
2-WIRE SERIAL CONTROL REGISTER DETAILS
CHIP IDENTIFICATION
0x00—Bits[7:0] Chip Revision
An 8-bit value that reflects the current chip revision.
0x11—Bit[7] HSYNC Source
0 = HSYNC, 1 = SOG. The power-up default is 0. These
selections are ignored if Register 0x11, Bit 6 = 0.
0x11—Bit[6] HSYNC Source Override
0 = auto HSYNC source, 1 = manual HSYNC source. Manual
HSYNC source is defined in Register 0x11, Bit 7. The power-up
default is 0.
0x11—Bit[5] VSYNC Source
0 = VSYNC, 1 = VSYNC from SOG. The power-up default is 0.
These selections are ignored if Register 0x11, Bit 4 = 0.
0x11—Bit[4] VSYNC Source Override
0 = auto VSYNC source, 1 = manual VSYNC source. Manual
VSYNC source is defined in Register 0x11, Bit 5. The power-up
default is 0.
0x11—Bit[3] Channel Select
0 = Channel 0, 1 = Channel 1. The power-up default is 0. These
selections are ignored if Register 0x11, Bit 2 = 0.
0x11—Bit[2] Channel Select Override
0 = auto channel select, 1 = manual channel select. Manual
channel select is defined in Register 0x11, Bit 3. The power-up
default is 0.
0x11—Bit[1] Interface Select
0 = analog interface, 1 = digital interface. The power-up default
is 0. These selections are ignored if Register 0x11, Bit 0 = 0.
0x11—Bit[0] Interface Select Override
0 = auto interface select, 1 = manual interface select. Manual
interface select is defined in Register 0x11, Bit 1. The power-up
default is 0.
0x12—Bit[7] Input HSYNC Polarity
0 = active low, 1 = active high. The power-up default is 1. These
selections are ignored if Register 10x2, Bit 6 = 0.
0x12—Bit[6] HSYNC Polarity Override
0 = auto HSYNC polarity, 1 = manual HSYNC polarity.
Manual HSYNC polarity is defined in Register 0x11, Bit 7.
The power-up default is 0.
0x12—Bit[5] Input VSYNC Polarity
0 = active low, 1 = active high. The power-up default is 1. These
selections are ignored if Register 0x11, Bit 4 = 0.
0x12—Bit[4] VSYNC Polarity Override
0 = auto VSYNC polarity, 1 = manual VSYNC polarity. Manual
VSYNC polarity is defined in Register 0x11, Bit 5. The power-
up default is 0.
0x17—Bits[3:0] HSYNCs per VSYNC MSBs
The 4 MSBs of the 12-bit counter that reports the number of
HSYNCs/VSYNC on the active input. This is useful in
determining the mode and aid in setting the PLL divide ratio.
0x18—Bit[7:0] HSYNCs per VSYNC LSBs
The 8 LSBs of the 12-bit counter that reports the number of
HSYNCs/VSYNC on the active input.
0x21—Bit[5] VSYNC Filter Enable
The purpose of the VSYNC filter is to guarantee the position of
the VSYNC edge with respect to the HSYNC edge and to
generate a field signal. The filter works by examining the
placement of VSYNC and regenerating a correctly placed
VSYNC one line later. The VSYNC is first checked to see
whether it occurs in the Field 0 position or the Field 1 position.
This is done by checking the leading edge position against the
sync separator threshold and the HSYNC position. The HSYNC
width is divided into four quadrants with Quadrant 1 starting at
the HSYNC leading edge plus a sync separator threshold. If the
VSYNC leading edge occurs in Quadrant 1 or Quadrant 4, the
field is set to 0 and the output VSYNC is placed coincident with
the HSYNC leading edge. If the VSYNC leading edge occurs in
Quadrant 2 or Quadrant 3, the field is set to 1 and the output
VSYNC leading edge is placed in the center of the line. In this
way, the VSYNC filter creates a predictable relative position
between HSYNC and VSYNC edges at the output.
If the VSYNC occurs near the HSYNC edge, this guarantees
that the VSYNC edge follows the HSYNC edge. This performs
filtering also in that it requires a minimum of 64 lines between
VSYNCs. The VSYNC filter cleans up extraneous pulses that
might occur on the VSYNC. This should be enabled whenever
the HSYNC/VSYNC count is used. Setting this bit to 0 disables
the VSYNC filter. Setting this bit to 1 enables the VSYNC filter.
Power-up default is 0.
0x21—Bit[4] VSYNC Duration Enable
This enables the VSYNC duration block which is designed to
be used with the VSYNC filter. Setting the bit to 0 leaves the
VSYNC output duration unchanged; setting the bit to 1 sets the
VSYNC output duration based on Register 0x22. The power-up
default is 0.
0x22—Bits[7:0] VSYNC Duration
This is used to set the output duration of the VSYNC, and is
designed to be used with the VSYNC filter. This is valid only if
Register 0x21, Bit 4 is set to 1. Power-up default is 4.
AD9398
Rev. 0 | Page 26 of 44
0x23—Bits[7:0] HSYNC Duration
An 8-bit register that sets the duration of the HSYNC output
pulse. The leading edge of the HSYNC output is triggered by
the internally generated, phase-adjusted PLL feedback clock.
The AD9398 then counts a number of pixel clocks equal to the
value in this register. This triggers the trailing edge of the
HSYNC output, which is also phase-adjusted. The power-up
default is 32.
0x24—Bit[7] HSYNC Output Polarity
This bit sets the polarity of the HSYNC output. Setting this bit
to 0 sets the HSYNC output to active low. Setting this bit to 1
sets the HSYNC output to active high. The power-up default
setting is 1.
0x24—Bit[6] VSYNC Output Polarity
This bit sets the polarity of the VSYNC output (both DVI and
analog). Setting this bit to 0 sets the VSYNC output to active
low. Setting this bit to 1 sets the VSYNC output to active high.
Power-up default is 1.
0x24—Bit[5] Display Enable Output Polarity
This bit sets the polarity of the display enable (DE) for both
DVI and analog. 0 = DE output polarity is negative. 1 = DE
output polarity is positive. The power-up default is 1.
0x24—Bit[4] Field Output Polarity
This bit sets the polarity of the field output signal on Pin 21.
0 = active low = even field; active high = odd field. 1 = active
low = odd field; active high = even field. The power-up default
setting is 1.
0x24—Bit[0] Output Clock Invert
This bit allows inversion of the output clock as specified by
Register 0x25, Bit 7 to Bit 6. 0 = noninverted clock. 1 = inverted
clock. The power-up default setting is 0.
0x25—Bits[7:6] Output Clock Select
These bits select the clock output on the DATACLK pin. They
include ½× clock, a 2× clock, a 90° phase shifted clock, or the
normal pixel clock. The power-up default setting is 01.
Table 12. Output Clock Select
Select Result
00 ½× pixel clock
01 1× pixel clock
10 2× pixel clock
11 90° phase 1× pixel clock
0x25—Bits[5:4] Output Drive Strength
These two bits select the drive strength for all the high speed
digital outputs (except VSOUT, A0, and O/E FIELD). Higher
drive strength results in faster rise/fall times and in general
makes it easier to capture data. Lower drive strength results in
slower rise/fall times and helps to reduce EMI and digitally
generated power supply noise. The power-up default setting is 11.
Table 13. Output Drive Strength
Output Drive Result
00 Low output drive strength
01 Medium low output drive strength
10 Medium high output drive strength
11 High output drive strength
0x25—Bits[3:2] Output Mode
These bits choose between four options for the output mode,
one of which is exclusive to an HDMI input. 4:4:4 mode is
standard RGB; 4:2:2 mode is YCrCb, which reduces the number
of active output pins from 24 to 16; 4:4:4 is double data rate
(DDR) output mode; and the data is RGB mode that changes on
every clock edge. The power-up default setting is 00.
Table 14. Output Mode
Output
Mode
Result
00 4:4:4 RGB mode
01 4:2:2 YCrCb mode + DDR 4:2:2 on blue (secondary)
10
DDR 4:4:4: DDR mode + DDR 4:2:2 on blue
(secondary)
11 12-bit 4:2:2 (HDMI option only)
0x25—Bit[1] Primary Output Enable
This bit places the primary output in active or high impedance
mode. The primary output is designated when using either 4:2:2
or DDR 4:4:4. In these modes, the data on the red and green
output channels is the primary output, while the output data
on the blue channel (DDR YCrCb) is the secondary output.
0 = primary output is in high impedance mode. 1 = primary
output is enabled. The power-up default setting is 1.
0x25—Bit[0] Secondary Output Enable
This bit places the secondary output in active or high impe-
dance mode. The secondary output is designated when using
either 4:2:2 or DDR 4:4:4. In these modes, the data on the blue
output channel is the secondary output, while the output data
on the red and green channels is the primary output. Secondary
output is always a DDR YCrCb data mode. 0 = secondary
output is in high impedance mode. 1 = secondary output is
enabled. The power-up default setting is 0.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

AD9398/PCBZ

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Buy AD9398/PCBZ
Manufacturer:
Analog Devices Inc.
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BOARD EVALUATION FOR AD9398
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