OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD9398/PCBZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
AD9398
Rev. 0 | Page 27 of 44
0x26—Bit[7] Output Three-State
When enabled, this bit puts all outputs (except SOGOUT) in a
high impedance state. 0 = normal outputs. 1 = all outputs
(except SOGOUT) in high impedance mode. The power-up
default setting is 0.
0x26—Bit[5] S/PDIF Three-State
When enabled, this bit places the S/PDIF audio output pins in a
high impedance state. 0 = normal S/PDIF output. 1 = S/PDIF
pins in high impedance mode. The power-up default setting is
0.
0x26—Bit[4] I
2
S Three-State
When enabled, this bit places the I
2
S output pins in a high
impedance state. 0 = normal I
2
S output. 1 = I
2
S pins in high
impedance mode. The power-up default setting is 0.
0x26—Bit[3] Power-Down Polarity
This bit defines the polarity of the input power-down pin.
0 = power-down pin is active low. 1 = power-down pin is active
high. The power-up default setting is 1.
0x26—Bits[2:1] Power-Down Pin Function
These bits define the different operational modes of the power-
down pin. These bits are functional only when the power-down
pin is active; when it is not active, the part is powered up and
functioning. 0 = the chip is powered down and all outputs are in
high impedance mode. 1 = the chip remains powered up, but all
outputs are in high impedance mode. The power-up default
setting is 00.
0x26—Bit[0] Power-Down
This bit is used to put the chip in power-down mode. In this
mode, the power dissipation is reduced to a fraction of the
typical power (see
Table 1 for exact power dissipation). When in
power-down, the HSOUT, VSOUT, DATACK, and all 30 of the
data outputs are put into a high impedance state. Note that the
SOGOUT output is not put into high impedance. Circuit blocks
that continue to be active during power-down include the
voltage references, sync processing, sync detection, and the
serial register. These blocks facilitate a fast start-up from power-
down. 0 = normal operation. 1 = power-down. The power-up
default setting is 0.
0x27—Bit[7] Auto Power-Down Enable
This bit enables the chip to go into low power mode, or seek
mode if no sync inputs are detected. 0 = auto power-down
disabled. 1 = chip powers down if no sync inputs present. The
power-up default setting is 1.
0x27—Bit[6] HDCP A0 Address
This bit sets the LSB of the address of the HDCP I
2
C. This
should be set to 1 only for a second receiver in a dual-link
configuration. The power-up default is 0.
0x27—Bit[5] MCLK External Enable
This bit enables the MCLK to be supplied externally. If an
external MCLK is used, then it must be locked to the video
clock according to the CTS and N available in the I
2
C. Any
mismatch between the internal MCLK and the input MCLK
results in dropped or repeated audio samples. 0 = use internally
generated MCLK. 1 = use external MCLK input. The power-up
default setting is 0.
BT656 GENERATION
0x27—Bit[4] BT656 Enable
This bit enables the output to be BT656 compatible with the
defined start of active video (SAV) and the end of active video
(EAV) controls to be inserted. These require specification of the
number of active lines, active pixels per line, and delays to place
these markers. 0 = disable BT656 video mode. 1 = enable BT656
video mode. The power-up default setting is 0.
0x27—Bit[3] Force DE Generation
This bit allows the use of the internal DE generator in DVI
mode. 0 = internal DE generation disabled. 1 = force DE
generation via programmed registers. The power-up default
setting is 0.
0x27—Bits[2:0] Interlace Offset
These bits define the offset in HSYNCs from Field 0 to Field 1.
The power-up default setting is 000.
0x28—Bits[7:2] VSYNC Delay
These bits set the delay (in lines) from the leading edge of
VSYNC to active video. The power-up default setting is 24.
0x28—Bits[1:0] HSYNC Delay MSBs
Together with Register 0x29, these 10 bits set the delay (in
pixels) from the HSYNC leading edge to the start of active
video. The power-up default setting is 0x104.
0x29—Bits[7:0] HSYNC Delay LSBs
See the HSYNC Delay MSBs section.
0x2A—Bits[3:0] Line Width MSBs
Together with Register 0x2B, these 12 bits set the width of
the active video line (in pixels). The power-up default setting
is 0x500.
0x2B—Bits[7:0] Line Width LSBs
See the Line Width MSBs section.
0x2C—Bits[3:0] Screen Height MSBs
Along with the 8 bits following these 12 bits, set the height of
the active screen (in lines). The power-up default setting is
0x2D0.
0x2D—Bits[7:0] Screen Height LSBs
See the Screen Heights MSBs section.
AD9398
Rev. 0 | Page 28 of 44
0x2E—Bit[7] Ctrl Enable
When set, this bit allows Ctrl [3:0] signals decoded from the
DVI to be output on the I
2
S data pins. 0 = I
2
S signals on I
2
S
lines. 1 = Ctrl[3:0] output on I
2
S lines. The power-up default
setting is 0.
0x2E—Bits[6:5] I
2
S Output Mode
These bits select between four options for the I
2
S output: I
2
S,
right-justified, left-justified, or raw IEC60958 mode. The
power-up default setting is 00.
Table 15. I
2
S Output Select
I
2
S Output Mode Result
00 I
2
S mode
01 Right-justified
10 Left-justified
11 Raw IEC60958 mode
0x2E—Bits[4:0] I
2
S Bit Width
These bits set the I
2
S bit width for right-justified mode. The
power-up default setting is 24 bits.
0x2F—Bit[6] TMDS Sync Detect
This read-only bit indicates the presence of a TMDS DE.
0 = no TMDS DE present. 1 = TMDS DE detected.
0x2F—Bit[5] TMDS Active
This read-only bit indicates the presence of a TMDS clock.
0 = no TMDS clock present. 1 = TMDS clock detected.
0x2F—Bit[4] AV Mute
This read-only bit indicates the presence of AV mute based on
general control packets. 0 = AV not muted. 1 = AV muted.
0x2F—Bit[3] HDCP Keys Read
This read-only bit reports if the HDCP keys were read
successfully. 0 = failure to read HDCP keys. 1 = HDCP keys
read.
0x2F—Bits[2:0] HDMI Quality
These read-only bits indicate a level of HDMI quality based on
the DE (display enable) edges. A larger number indicates a
higher quality.
0x30—Bit[6] HDMI Content Encrypted
This read-only bit is high when HDCP decryption is in use
(content is protected). The signal goes low when HDCP is not
being used. Customers can use this bit to determine whether to
allow copying of the content. The bit should be sampled at
regular intervals because it can change on a frame-by-frame
basis. 0 = HDCP not in use. 1 = HDCP decryption in use.
0x30—Bit[5] DVI HSYNC Polarity
This read-only bit indicates the polarity of the DVI HSYNC.
0 = DVI HSYNC polarity is low active. 1 = DVI HSYNC
polarity is high active.
0x30—Bit[4] DVI VSYNC Polarity
This read-only bit indicates the polarity of the DVI VSYNC.
0 = DVI VSYNC polarity is low active. 1 = DVI VSYNC polarity
is high active.
0x30—Bits[3:0] HDMI Pixel Repetition
These read-only bits indicate the pixel repetition on DVI.
0 = 1×, 1 = 2×, 2 = 3×, up to a maximum repetition of
10× (0x9).
Table 16.
Select Repetition Multiplier
0000 1×
0001 2×
0010 3×
0011 4×
0100 5×
0101 6×
0110 7×
0111 8×
1000 9×
1001 10×
MACROVISION
0x31—Bits[7:4] Macrovision Pulse Max
These bits set the pseudo sync pulse width maximum for
Macrovision detection in pixel clocks. This is functional for
13.5 MHz SDTV or 27 MHz progressive scan. Power-up
default is 9.
0x31—Bits[3:0] Macrovision Pulse Min
These bits set the pseudo sync pulse width maximum for
Macrovision detection in pixel clocks. This is functional for
13.5 MHz SDTV or 27 MHz progressive scan. Power-up
default is 6.
0x32—Bit[7] Macrovision Oversample Enable
Tells the Macrovision detection engine whether oversampling
is used. This accommodates 27 MHz sampling for SDTV and
54 MHz sampling for progressive scan and is used as a
correction factor for clock counts. Power-up default is 0.
0x32—Bit[6] Macrovision PAL Enable
Tells the Macrovision detection engine to enter PAL mode when
set to 1. Default is 0 for NTSC mode.
0x32—Bit[5:0] Macrovision Line Count Start
Set the start line for Macrovision detection. Along with
Register 0x33, Bits [5:0], they define the region where MV
pulses are expected to occur. The power-up default is Line 13.
AD9398
Rev. 0 | Page 29 of 44
0x33—Bit[7] Macrovision Detect Mode
0 = standard definition. 1 = progressive scan mode.
0x33—Bit[6] Macrovision Settings Override
This defines whether preset values are used for the MV line
counts and pulse widths or the values stored in I
2
C registers.
0 = use hard-coded settings for line counts and pulse widths.
1 = use I
2
C values for these settings.
0x33—Bits[5:0] Macrovision Line Count End
Set the end line for Macrovision detection. Along with
Register 0x32, Bits[5:0], they define the region where MV
pulses are expected to occur. The power-up default is Line 21.
0x34—Bits[7:6] Macrovision Pulse Limit Select
Set the number of pulses required in the last three lines (SD
mode only). If there is not at least this number of MV pulses,
the engine stops. These 2 bits define the following pulse counts:
00 = 6
01 = 4
10 = 5 (default)
11 = 7
0x34—Bit[5] Low Frequency Mode
Sets whether the audio PLL is in low frequency mode or
not. Low frequency mode should only be set for pixel clocks
< 80 MHz.
0x34—Bit[4] Low Frequency Override
Allows the previous bit to be used to set low frequency mode
rather than the internal auto-detect.
0x34—Bit[3] Up Conversion Mode
0 = repeat Cb/Cr values. 1 = interpolate Cb/Cr values.
0x34—Bit[2] CbCr Filter Enable
Enables the FIR filter for 4:2:2 CbCr output.
COLOR SPACE CONVERSION
The default power-up values for the color space converter
coefficients (R0x35 through R0x4C) are set for ATSC RGB-to-
YCbCr conversion. They are completely programmable for
other conversions.
0x34—Bit[1] Color Space Converter Enable
This bit enables the color space converter. 0 = disable color
space converter. 1 = enable color space converter. The power-up
default setting is 0.
0x35—Bits[6:5] Color Space Converter Mode
These two bits set the fixed-point position of the CSC
coefficients, including the A4, B4, and C4 offsets.
Table 17. CSC Fixed Point Converter Mode
Select Result
00 ±1.0, −4096 to +4095
01 ±2.0, −8192 to +8190
1× ±4.0, −16384 to +16380
0x35—Bits[4:0] Color Space Conversion Coefficient A1
MSBs
These 5 bits form the 5 MSBs of the Color Space Conversion
Coefficient A1. This combined with the 8 LSBs of the following
register form a 13-bit, twos complement coefficient that is user
programmable. The equation takes the form of:
R
OUT
= (A1 × R
IN
) + (A2 × G
IN
) + (A3 × B
IN
) + A4
G
OUT
= (B1 × R
IN
) + (B2 × G
IN
) + (B3 × B
IN
) + B4
B
OUT
= (C1 × R
IN
) + (C2 × G
IN
) + (C3 × B
IN
) + C4
The default value for the 13-bit A1 coefficient is 0x0C52.
0x36—Bits[7:0] Color Space Conversion Coefficient A1
LSBs
See the Register 0x35[4:0] section.
0x37—Bits[4:0] CSC A2 MSBs
These five bits form the 5 MSBs of the Color Space Conversion
Coefficient A2. Combined with the 8 LSBs of the following
register, they form a 13-bit, twos complement coefficient that is
user programmable. The equation takes the form of:
R
OUT
= (A1 × R
IN
) + (A2 × G
IN
) + (A3 × B
IN
) + A4
G
OUT
= (B1 × R
IN
) + (B2 × G
IN
) + (B3 × B
IN
) + B4
B
OUT
= (C1 × R
IN
) + (C2 × G
IN
) + (C3 × B
IN
) + C4
The default value for the 13-bit A2 coefficient is 0x0800.
0x38—Bits[7:0] CSC A2 LSBs
See the Register 0x37 section.
0x39—Bits[4:0] CSC A3 MSBs
The default value for the 13-bit A3 is 0x0000.
0x3A—Bits[7:0] CSC A3 LSBs
0x3B—Bits[4:0] CSC A4 MSBs
The default value for the 13-bit A4 is 0x19D7.
0x3C—Bits[7:0] CSC A4 LSBs
0x3D—Bits[4:0] CSC B1 MSBs
The default value for the 13-bit B1 is 0x1C54.
0x3E—Bits[7:0] CSC B1 LSBs
0x3F—Bits[4:0] CSC B2 MSB
The default value for the 13-bit B2 is 0x0800.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

AD9398/PCBZ

Mfr. #:
Buy AD9398/PCBZ
Manufacturer:
Analog Devices Inc.
Description:
BOARD EVALUATION FOR AD9398
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet