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DS2180AQN

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DS2180A
19 of 35
RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 18
(MSB) (LSB)
BVCS ECS RYEL RCL FERR B8ZSD RBL RLOS
SYMBOL POSITION NAME AND DESCRIPTION
BVCS RIMR.7
Bipolar Violation Count Saturation Mask.
1 = Interrupt masked.
0 = Interrupt masked.
ECS RIMR.6
Error Count Saturation Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
RYEL RIMR.5
Receive Yellow Alarm Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
RCL RIMR.4
Receive Carrier Loss Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
FERR RIMR.3
Frame Bit Error Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
B8ZSD
RIMR.2
B8ZS Detect Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
RBL RIMR.1
Receive Blue Alarm Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
RLOS
RIMR.0
Receive Loss of Sync Mask.
1 = Interrupt enabled.
0 = Interrupt masked.
ALARM COUNTERS
The three onboard alarm event counters allow the transceiver to monitor and record error events without
processor intervention on each event occurrence. All of these counters are presettable by the user
establishing an event count interrupt threshold. As each counter saturates, the next error event occurrence
will set a bit in the RSR and generate an interrupt unless masked. The user may read these registers at any
time; in many systems, the host will periodically poll these registers to establish link error rate
performance.
OOF EVENTS AND ERRORED
SUPERFRAMES
Out of frame is declared when at least two of four (or five) consecutive framing bits are in error. F
T
bits
are tested for OOF occurrence in 193S; the FPS bits are tested in 193E. OOF events are recorded by the
4-bit OOF counter in the error counter register. In the 193E framing mode, the OOF event is logically
OR’ed with an on-chip generated CRC checksum. This event, known as errored superframe, is recorded
by the 4-bit ESF error counter in the error count register. In the 193S framing mode, the 4-bit ESF error
counter records individual F
T
and F
S
errors when RCR.3=1 or F
T
errors only when RCR.3=0.
DS2180A
20 of 35
BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 19
(MSB) (LSB)
BVD7 BVD6 BVD5 BVD4 BVD3 BVD2 BVD1 BVD0
SYMBOL POSITION NAME AND DESCRIPTION
BVD7 BVCR.7 MSB of bipolar count.
BDV0 BVCR.0 LSB of bipolar count.
This 8-bit binary up counter saturates at 255 and will generate an interrupt for each occurrence of a
bipolar violation once saturated (RIMR.7=1). Presetting this register allows the user to establish specific
count interrupt thresholds. The counter will count “up” to saturation from the preset valued and may be
read at any time. Counter increments occur at all times and are not disabled by resync. If B8ZS is enabled
(CCR.2=1) bipolar violations are not counted for B8ZS code words.
ECR: ERROR COUNT REGISTER Figure 20
(MSB) (LSB)
OOFD3 OOFD2 OOFD1 OOFD0 ESFD3 ESFD2 ESFD1 ESFD0
ERROR COUNT ESF ERROR COUNT
SYMBOL POSITION NAME AND DESCRIPTION
OOFD3 ECR.7 MSB of OOF event count.
OOFD0 ECR.4 LSB of OOF event count.
ESDF3 ECR.3 MSB of extended superframe error count.
ESFD0 ECR.0 LSB of extended superframe error count.
These separate 4-bit binary up counters saturate at a count of 15 and will generate an interrupt for each
occurrence of an OOF event or an ESF error event after saturation (RIMR.6=1). Presetting these counters
allows the user to establish specific count interrupt thresholds. The counters will count “up” to saturation
from the preset value and may be read at any time. These counters share the same register address and
must be written to or read from simultaneously.
The OOF counter records out-of-frame events in both 193S and 193E. The ESF error counter records
errored superframes in 193E. In 193S, the ESF counter records individual F
T
and F
S
errors when
RCR.3=1; F
T
errors only when RCR.3=0. ECR counter increments are disabled when resync is in
progress (RLOS high).
ALARM OUTPUTS
The transceiver also provides direct alarm outputs for applications when additional decoding and
demuxing are required to supplement the onboard alarm logic.
RLOS OUTPUT
The receive loss of sync output indicates the status of the receiver synchronizer circuitry; when high, an
off-line resynchronization is in progress and a high-low transition indicates resync is complete. The
RLOS bit (RSR.0) is a “latched” version of the RLOS output. If the auto-resync mode is selected
(RCR.1=0), RLOS is a real time indication of a carrier loss or OOF event occurrence.
DS2180A
21 of 35
RYEL OUTPUT
The yellow alarm output transitions high when a yellow alarm is detected. A high-low transition indicates
the alarm condition has been cleared. The RYEL bit (RSR.5) is a “latched” version of the RYEL output.
In 193E framing, the yellow alarm pattern detected is 16 pattern sets of 00 (Hex) and FF (Hex) received
at RLINK. In 193S, framing the yellow alarm format is de-pendent on CCR.3; if CCR.3=0, the RYEL
output transitions high if bit 2 of 256 or more consecutive channels is 0; if CCR.3=1, yellow alarm is
declared when the S-bit received in frame 12 is 1.
RBV OUTPUT
The bipolar violation output transitions high when an accused bit emerges at RSER. RBV will go low at
the next bit time if no additional violations are detected.
RFER OUTPUT
The receive frame error output transitions high at the F-bit time and is held high for two bit periods when
a frame bit error occurs. In 193S framing, F
T
and F
S
patterns are tested. The FPS pattern is tested in 193E
framing. Additionally, in 193E framing, RFER reports a CRC error by a low-high-low transition (one bit
period wide) one half RCLK period before a low-high transition on RMSYNC.
RESET
A high-low transition on RST clears all registers and forces immediate receive resync when RST returns
high. This reset has no effect on transmit frame multiframe or channel counters. RST must be held low on
system power-up to insure proper initialization of transceiver counters and registers. Following reset, the
host processor should restore all control modes by writing appropriate registers with control data.
ALARM OUTPUT TIMING Figure 21
NOTES:
1. RFER transitions high during F-bit time if received framing pattern bit is in error. (Frame 12 F-bits in
193S are ignored if CCR.3=1). Also, in 193E, RFER transitions 1/2 bit time before the rising edge of
RMSYNC to indicate a CRC error for the previous multiframe.
2. RBV indicates received bipolar violation and transitions high when an accused bit emerges from
RSER. If B8ZS is enabled, RBV will not report the zero replacement code.
3. RCL transitions high (during 32nd bit time) when 32 consecutive bits received are 0; RCL transitions
low when the next 1 is received.
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DS2180AQN

Mfr. #:
Buy DS2180AQN
Manufacturer:
Maxim Integrated
Description:
Telecom Interface ICs T1 Transceiver
Lifecycle:
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