DS2180A
28 of 35
PROCESSOR-BASED TRANSMIT SIGNALING INSERTION Figure 23
PROCESSOR-BASED SIGNALING
Many robbed-bit signaling applications utilize a microprocessor to insert transmit signaling data into the
out-going data stream. The circuit shown in Figure 23 “decouples” the processor timing from that of the
DS2180A by use of a small FIFO memory. The processor writes to the FIFO (6 bytes are written: 3 for A
data, 3 for B data) only when signaling updates are required. The system is interrupt-driven from the
transmit multiframe sync input; the processor must update the FIFO prior to Frame 6 (625 µs after
interrupt) to prevent data corruption. The application circuit shown supports 193S framing. Additional
hardware is required for 193E applications.
DS2180A
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature 0° to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Logic 1 V
IH
2.0 V
DD
+.3 V
Input Logic 0 V
IL
-0.3 +0.8 V
Supply V
DD
4.5 5.0 5.5 V
CAPACITANCE (t
A
=25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance C
IN
5pF
Output Capacitance C
OUT
7pF
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; V
DD
= 5.0V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Current I
DD
3 10 mA 1,2
Input Leakage I
IL
1 µA
Output Leakage I
LO
A 3
Output Current @ 2.4V I
OH
-1 mA 4
Output Current @ .4V I
OL
+4 mA 5
NOTES:
1. TCLK = RCLK = 1.544 MHz.
2. Outputs open.
3. Applies to SDO when tri-stated.
4. All outputs except
INT , which is open collector.
5. All outputs.
DS2180A
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AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; V
DD
= 5.0V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
SDI to SCLK Setup t
CC
50 ns
SCLK to SDI Hold t
CDH
50 ns
SDI to SCLK Falling Edge t
CD
50 ns
SCLK Low Time t
CL
250 ns
SCLK High Time t
CH
250 ns
SCLK Rise and Fall Time t
R,
t
F
500 ns
CS to SCLK Setup
t
CC
50 ns
SCLK to CS Hold
t
CCH
50 ns
CS Inactive Time
t
CWH
250 ns
ACLK to SDO Valid
2
t
CDV
200 ns
CS to SDO High Z
t
CDZ
75 ns
SCLK Setup toCS Falling
T
SCC
50 ns
NOTES:
1. Measured at V
IH
=2.0 V; V
IL
=.8 V and 10 ns maximum rise and fall time.
2. Output load capacitance = 100 pF.
SERIAL PORT WRITE AC TIMING DIAGRAM
NOTES:
1. Data byte bits must be valid across low clock periods to prevent transients in operating modes.
2. Shaded regions indicate “don’t care” states of input data.

DS2180AQN

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Telecom Interface ICs T1 Transceiver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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