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DS2180AQN

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DS2180A
22 of 35
4. RLOS transitions high during the F-bit time that caused an OOF event (any two of four consecutive
F
T
or FPS bits are in error) if auto-resync mode is selected (RCR.1=0). Resync will also occur when
loss of carrier is detected (RCL=1). When RCR.1=1, RLOS remains low until resync occurs,
regardless of OOF or carrier loss flags. In this situation, resync is initiated only when RCR.0
transitions low-to-high or the RST pin transitions high-low-high.
HARDWARE MODE
For preliminary system prototyping or applications which do not require the features offered by the serial
port, the transceiver can be reconfigured by the SPS pin. Tying SPS to V
SS
disables the serial port, clears
all internal registers except CCR and TCR and redefines pins 14 through 18 as mode control inputs. The
hardware mode allows device retrofit into existing applications where mode control and alarm
conditioning hardware is often designed with discrete logic.
HARDWARE COMMON CONTROL
In the hardware mode bits TCR.2, CCR.4, TCR.0, CCR.1 and CCR.2 map to pins 14 through 18. The
loop-back feature (bit CCR.0) is enabled by tying pins 17 (zero suppression) and 18 (B8ZS) to 1. (The
last states of pins 17 and 18 are latched as when both pins are taken high, preserving the current zero
suppression mode). Robbed bit signaling (bit TCR.4) is enabled for all channels. The user may tie TSER
to TABCD externally to disable signaling if so desired. Bit CCR.3 is forced to 0 which selects bit 2
yellow alarm in 193S framing. Contents of the RCR, as well as the remaining bit locations in the CCR
and TCR are cleared in the hardware mode. The RST input may be used to force immediate receiver
resync and has no effect on transmit.
HARDWARE MODE Table 6
PIN
NUMBER
REGISTER BIT
LOCATION
NAME AND DESCRIPTION
14 (16) TCR-D2
193S – S-bit insertion
3
1 = external; 0 = internal
15 (17) CCR-D4
Framing Mode Select.
1 = 193E; 0 = 193S
16 (18) TCR-D0
Transmit Yellow Alarm
2 ,3
1 = enabled; 0 = disabled
17 (19) CCR-D1
Zero Suppression
1
1 = bit 7 stuffing
0 = transparent
18 (20) CCR-D2
B8ZS
1
1 = enabled; 0 = disabled
NOTES
1. Tying pins 17 and 18 high enables loopback in the hardware mode.
2. Bit 2 (193S) and data link (193E) yellow alarms are supported.
3. S-bit yellow alarm (193S) is not internally supported; however, the user may elect to insert external S
bits for alarm purposes.
4. Pin numbers for PLCC package are listed in parenthesis.
DS2180A
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T1 OVERVIEW
Framing Standards
The DS2180A is compatible with the existing Bell System D4 framing standard described in ATT PUB
43801 and the new extended superframe format (ESF) as described in ATT C.B. #142. In this document,
D4 framing is referred to as 193S and ESF (also known as Fe) is referred to as 193E. Programmable
features of the DS2180A allow support of other framing standards which are derivatives of 193E and
193S. The salient differences between the 193S and 193E formats are the number of frames per
superframe and use of the F-bit position. In 193S, 12 frames make up a superframe, in 193E, 24. A frame
consists of 24 channels (timeslots) of 8-bit data preceded by an F-bit. Channel data is transmitted and
received MSB first.
F-Bits
The use of the F-bit position in 193S is split between the terminal framing pattern (know as F
T
-bits)
which pro-vides frame alignment information and the signaling framing pattern (known as F
S
-bits) which
provides multiframe alignment information. In 193E framing, the F-bit position is shared by the framing
pattern sequence (FPS) which provides frame and multiframe alignment information, a 4 kHz data link
known as FDL (Facility Data Link), and CRC (Cyclic Redundancy Check) bits. The FDL bits are used
for control and maintenance (inserted by the user at TLINK) and the CRC bits are an indicator of link
quality and may be monitored by the user to establish error performance.
Signaling
During frames 6 and 12 in 193S, A and B signaling information is inserted into the LSB of all channels
transmitted. In 193E, A and B data is inserted into frames 6 and 12 and C and D data is inserted into
frames 18 and 24. This allows a maximum of four signaling states to be transmitted per superframe in
193S and 16 states in 193E.
Alarms
The DS2180A supports all alarm pattern generation and detection required in typical Bell System
applications. These alarm modes are explained in ATT PUB 43801, ATT C.B. #142 and elsewhere in
this document.
DS2180A
24 of 35
193E FRAMING FORMAT Table 7
F-BIT USE BIT USE IN EACH CHANNEL SIGNALING-BIT USEFRAME
NUMBER
FPS
1
FPL
2
CRC
3
DATA SIGNALING 2
STATE
4
STATE
16
STATE
1-M-BITS 1-8
2--C1BITS 1-8
3-M-BITS 1-8
40--BITS 1-8
5-M-BITS 1-8
6 - - C2 BITS 1-7 BIT 8 A A A
7-M-BITS 1-8
80--BITS 1-8
9-M-BITS 1-8
10 - - C3 BITS 1-8
11 - M - BITS 1-8
12 1 - - BITS 1-7 BIT 8 A B B
13 - M - BITS 1-8
14 - - C4 BITS 1-8
15 - M - BITS 1-8
16 0 - - BITS 1-8
17 - M - BITS 1-8
18 - - C5 BITS 1-7 BIT 8 A C C
19 - M - BITS 1-8
20 1 - - BITS 1-8
21 - M - BITS 1-8
22 - - C6 BITS 1-8
23 - M - BITS 1-8
24 1 - - BITS 1-7 BIT 8 A B D
NOTES:
1. FPS – Framing Pattern Sequence.
2. FDL – 4 kHz Facility Data Link; M = message bits.
3. CRC – Cyclic Redundancy Check bits. The CRC code will be internally generated by the device
when TCR.5=0. When TCR.5=1, externally supplied CRC data will be sampled at TSER during the
F-bit time of frames 2, 6, 10, 14, 18, 22.
4. The user may program any individual channels clear, in which case bit 8 will be used for data, not
signaling.
5. Depending on application, the user can support 2-state, 4-state or 16-state signaling by the appropriate
decodes of TMO, TSIGFR, TSIGSEL (Transmit Side) and RMSYNC, RSIGFR and RSIGSEL
(Receive Side).
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DS2180AQN

Mfr. #:
Buy DS2180AQN
Manufacturer:
Maxim Integrated
Description:
Telecom Interface ICs T1 Transceiver
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