MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
19
Maxim Integrated
external bypass capacitor and works best when left
unconnected (SEL1 = 0).
External Reference
The external reference can range from 1V to V
DD
. For
maximum conversion accuracy, the reference must be
able to deliver up to 40µA and have an output imped-
ance of 500Ω or less. If the reference has a higher out-
put impedance or is noisy, bypass it to GND as close
as possible to AIN_/REF with a 0.1µF capacitor.
Transfer Functions
Output data coding for the MAX11606–MAX11611 is
binary in unipolar mode and two’s complement in bipo-
lar mode with 1LSB = (V
REF
/2N) where N is the number
of bits (10). Code transitions occur halfway between
successive-integer LSB values. Figure 12 and Figure
13 show the input/output (I/O) transfer functions for
unipolar and bipolar operations, respectively.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not
recommended since the layout should ensure proper
separation of analog and digital traces. Do not run ana-
log and digital lines parallel to each other, and do not
layout digital signal paths underneath the ADC pack-
age. Use separate analog and digital PCB ground sec-
tions with only one star point (Figure 14) connecting the
two ground systems (analog and digital). For lowest
noise operation, ensure the ground return to the star
ground’s power supply is low impedance and as short
as possible. Route digital signals far away from sensi-
tive analog and reference inputs.
High-frequency noise in the power supply (V
DD
) could
influence the proper operation of the ADC’s fast com-
parator. Bypass V
DD
to the star ground with a network of
two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX11606–MAX11611 power-
supply pin. Minimize capacitor lead length for best sup-
ply noise rejection, and add an attenuation resistor (5Ω)
in series with the power supply, if it is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once offset
and gain errors have been nullified. The MAX11606–
MAX11611’s INL is measured using the endpoint.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples.
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS
0
INPUT VOLTAGE (LSB)
OUTPUT CODE
ZS = 0
+FS - 1 LSB
*V
COM
V
REF
/2 *V
IN
= (AIN+) - (AIN-)
FS
=
V
REF
2
-FS =
-V
REF
2
MAX11606–
MAX11611
1 LSB =
V
REF
1024
Figure 13. Bipolar Transfer Function
GND
V
LOGIC
= 3V/5V3V OR 5V
SUPPLIES
DGND3V/5VGND
*OPTIONAL
4.7μF
R* = 5Ω
0.1μF
V
DD
DIGITAL
CIRCUITRY
MAX11606–
MAX11611
Figure 14. Power-Supply Grounding Connection
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
20
Maxim Integrated
Aperture Delay
Aperture delay (t
AD
) is the time between the falling
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNR
MAX[dB]
= 6.02
dB
N + 1.76
dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20 log (SignalRMS/NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through V
5
are the amplitudes of the 2nd through 5th order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
THD
VVVV
V
+++
20
2
2
3
2
4
2
5
2
1
log
SINAD dB
SignalRMS
NoiseRMS THDRMS
( ) log
+
20
Chip Information
PROCESS: BiCMOS
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I
2
C,
10-Bit ADCs in Ultra-Small Packages
21
Maxim Integrated
*OPTIONAL
**AIN11/REF (MAX11610/MAX11611)
R
S
*
R
S
*
ANALOG
INPUTS
μC
SDA
SCL
GND
V
DD
SDA
SCL
AIN0
AIN1
RC NETWORK*
AIN3**/REF
3.3V or 5V
5V
R
P
C
REF
0.1μF
R
P
5V
MAX11606–
MAX11611
0.1μF
2kΩ
Typical Operating Circuit
SDA
SCLAIN3/REF
1
2
8
7
V
DD
GNDAIN1
AIN2
AIN0
µMAX
TOP VIEW
3
4
6
5
MAX11606
MAX11607
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
(REF) AIN11/REF V
DD
GND
SDA
SCL
AIN7
AIN6
AIN5
AIN4
( ) INDICATES PINS ON THE MAX11608/MAX11609.
MAX11608–
MAX11611
QSOP
+
+
(N.C.) AIN10
(N.C.) AIN9
AIN1
(N.C.) AIN8
AIN0
AIN2
AIN3
Pin Configurations
Selector Guide
PART
INPUT
CHANNELS
INTERNAL
REFERENCE
(V)
SUPPLY
VOLTAGE
(V)
INL
(LSB)
MAX11606 4 4.096 4.5 to 5.5 ±1
MAX11607 4 2.048 2.7 to 3.6 ±1
MAX11608 8 4.096 4.5 to 5.5 ±1
MAX11609 8 2.048 2.7 to 3.6 ±1
MAX11610 12 4.096 4.5 to 5.5 ±1
MAX11611 12 2.048 2.7 to 3.6 ±1
MAX11607
TOP VIEW
(BUMPS ON BOTTOM)
A
B
C
WLP
1234
AIN0
AIN1 AIN2
AIN3/
REF
GND
GND GND GND
V
DD
GND SDA SCL
+
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 µMAX U8CN+1
21-0036 90-0092
12 WLP W121C2+1
21-0009
Refer to Application
Note 1891
16 QSOP E16+1
21-0055 90-0167
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages
. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.

MAX11610EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 12Ch 94.4sps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
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